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| ? 1. general description the dac1617d1g0 is a high-speed 16-bit dual channel digital-to-analog converter (dac) with selectable ? 2, ? 4 and ? 8 interpolation filters. th e device is optimized for multi-carrier and broadband wireless transmitters at sample rates of up to 1 gsps. supplied from a 3.3 v and a 1.8 v source, the dac1617d1g0 integrates a differential scalable output current up to 34 ma. the serial peripheral interface (spi) pr ovides full control of the dac1617d1g0. the dac1617d1g0 integrates a low voltage differential signaling (lvds) double data rate (ddr) receiver interf ace, with an on-chip 100 ? termination. the lvds ddr interface accepts a multiplex input data stream such as interleaved or folded. an internal lvds input auto-calibration ensures the ro bustness and stabilit y of the interface. digital on-chip modulation converts the complex i and q inputs from baseband to if. a 40-bit numerically controlled oscillator (nco) sets the mixe r frequency. high resolution internal gain, phase and offset control provide outsta nding image and local oscillator (lo) signal rejection at the system analog modulator output. an inverse (sin x) / x function ensures a cont rolled flatness 0.5 db for high bandwidths at the dac output. multiple device synchronization allows synchronization of the outputs of multiple dac devices. mds guarantees a maximum skew of one output clock period between several devices. the dac1617d1g0 includes a very low noise capacitor-free integrated phase-locked loop (pll) multiplier which generates a dac clock rate from the lvds clock rate. the dac1617d1g0 is available in an hvqfn72 package (10 mm ? 10 mm). 2. features and benefits dac1617d1g0 dual 16-bit dac, lvds interface, up to 1 gsps, x2, x4 and x8 interpolating rev. 03 ? 2 july 2012 preliminary data sheet ? dual-channel 16-bit resolution ? synchronization of multiple dac devices ? 1 gsps maximum update rate ? 3-wire or 4-wire mode spi interface ? selectable ? 2, ? 4 and ? 8 interpolation filters ? differential scalable output current from 8.1 ma to 34 ma ? very low noise capacitor-free integrated phase-locked loop (pll) ? external analog offset control (10-bit auxiliary dacs)
dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 2 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 3. applications ? wireless infrastructure: lte, wimax, gsm, cdma, wcdma, td-scdma ? communications: lmds/mmds, point-to-point ? direct digital synthesis (dds) ? broadband wireless systems ? digital radio links ? instrumentation ? automated test equipment (ate) 4. ordering information ? embedded numerically controlled oscillator (nco) with 40-bit programmable frequency ? high resolution internal digital gain and offset control to support high performance iq-modulator image rejection ? embedded complex(i/q) digital if modulator ? internal phase correction ? 1.8 v and 3.3 v power supplies ? inverse (sin x) / x function ? lvds ddr compatible input interface with on-chip 100 ? terminations ? power-down mode and sleep mode; 5-bit nco low-power mode ? lvds ddr input clock up to 370 mhz ? on-chip 1.25 v reference ? lvds or lvpecl compatible dac clock ? industrial temperature range ? 40 ? c to +85 ? c ? interleaved or folded i and q data input mode ? 72 pins small form factor hvqfn package table 1. ordering information type number package name description version DAC1617D1G0HN hvqfn72 plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 ? 10 ? 0.85 mm sot813-3 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 3 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 5. block diagram fig 1. block diagram d d d , 2 8 7 % 3 , 2 8 7 % 1 , 2 8 7 $ 3 , 2 8 7 $ 1 $ 8 ; $ 3 $ 8 ; $ 1 v l q f r v 2 ) ) 6 ( 7 & 2 1 7 5 2 / ' $ & % ; v l q ; * $ 3 2 8 7 9 , 5 ( 6 ; v l q ; % , 7 $ 1 $ / 2 * * $ , 1 & 2 1 7 5 2 / % , 7 $ 1 $ / 2 * * $ , 1 & 2 1 7 5 2 / & / , 3 3 , 1 * & / , 3 3 , 1 * % , 7 2 ) ) 6 ( 7 & 2 1 7 5 2 / 1 & 2 e l w i u h t x h q f \ v h w w l q j e l w s k d v h d g m x v w p h q w % , 7 2 ) ) 6 ( 7 & 2 1 7 5 2 / 5 ( ) % $ 1 ' * $ 3 $ 1 ' % , $ 6 , 1 * ' $ & $ $ 8 ; ' $ & $ 8 ; % 3 $ 8 ; % 1 $ 8 ; ' $ & [ ) , 5 [ ) , 5 0 8 / 7 , ' $ & 6 < 1 & + 5 2 1 , = $ 7 , 2 1 [ ) , 5 [ ) , 5 [ ) , 5 [ ) , 5 & / 2 & . * ( 1 ( 5 $ 7 2 5 3 / / ' & 0 6 8 & ' , 6 3 , 6 ' 2 6 ' , 2 6 & 6 b 1 6 & / . 0 ' 6 & 2 $ 5 6 ( 3 + $ 6 ( & 2 0 3 ( 1 6 $ 7 , 2 1 ' , * , 7 $ / * $ , 1 2 ) ) 6 ( 7 / 9 ' 6 ' ' 5 ' , ) & / . 3 / ' & / . 1 / ' & / . 3 / ' 1 w r / ' 1 / ' 3 w r / ' 3 $ / , * 1 1 $ / , * 1 3 & / . 1 0 ' 6 3 0 ' 6 1 , 1 7 ( 5 5 8 3 7 , 1 7 ( 5 1 $ / 0 2 1 , 7 2 5 , 1 * , 2 , 2 5 ( 6 ( 7 b 1 ' $ & ' & 2 0 3 / ( ; 0 2 ' 8 / $ 7 2 5 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 4 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration d d d ' $ & ' * 7 u d q v s d u h q w w r s y l h z / ' > @ 1 / ' > @ 1 / ' > @ 3 / ' > @ 3 / ' > @ 3 / ' > @ 1 / ' > @ 1 / ' > @ 3 / ' > @ 3 / ' > @ 1 9 ' ' ' 9 ' ' ' / ' > @ 1 / ' > @ 3 / ' > @ 3 / ' > @ 1 / ' > @ 1 / ' > @ 3 / ' > @ 3 / ' > @ 1 $ / , * 1 1 , 2 $ / , * 1 3 , 2 7 0 6 ' 2 0 ' 6 1 6 ' , 2 0 ' 6 3 6 & / . & / . 1 6 & 6 b 1 / ' > @ 3 / ' > @ 1 / ' > @ 3 / ' > @ 1 / ' > @ 3 / ' > @ 1 9 ' ' ' / & . 3 / & . 1 q f / ' > @ 3 / ' > @ 1 / ' > @ 3 / ' > @ 1 / ' > @ 3 / ' > @ 1 , 2 8 7 $ 1 , 2 8 7 $ 3 9 ' ' $ 9 b ' 9 ' ' $ 9 $ 8 ; $ 3 $ 8 ; $ 1 9 ' ' $ 9 b 3 * $ 3 2 8 7 9 , 5 ( 6 9 ' ' $ 9 b 3 $ 8 ; % 1 $ 8 ; % 3 9 ' ' $ 9 9 ' ' $ 9 b ' , 2 8 7 % 3 , 2 8 7 % 1 / ' > @ 1 / ' > @ 3 & / . 3 5 ( 6 ( 7 b 1 9 ' ' ' 9 ' ' ' 9 ' ' $ 9 b ' 9 ' ' $ 9 b ' w h u p l q d o l q g h [ d u h d table 2. pin description symbol pin type [1] description clkp 1 i dac clock positive input clkn 2 i dac clock negative input mdsp 3 io multi-device synchronization positive signal mdsn 4 io multi-device synchr onization negative signal tm 5 i test mode selection (connect to gnd) alignp 6 i positive input for data alignment alignn 7 i negative input for data alignment ld[15]p 8 i lvds positive input bit 15 [2] ld[15]n 9 i lvds negative input bit 15 [2] dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 5 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating ld[14]p 10 i lvds positive input bit 14 [2] ld[14]n 11 i lvds negative input bit 14 [2] v ddd 12 p digital power supply ld[13]p 13 i lvds positive input bit 13 [2] ld[13]n 14 i lvds negative input bit 13 [2] ld[12]p 15 i lvds positive input bit 12 [2] ld[12]n 16 i lvds negative input bit 12 [2] ld[11]p 17 i lvds positive input bit 11 [2] ld[11]n 18 i lvds negative input bit 11 [2] v ddd 19 p digital power supply ld[10]p 20 i lvds positive input bit 10 [2] ld[10]n 21 i lvds negative input bit 10 [2] ld[9]p 22 i lvds positive input bit 9 [2] ld[9]n 23 i lvds negative input bit 9 [2] ld[8]p 24 i lvds positive input bit 8 [2] ld[8]n 25 i lvds negative input bit 8 [2] v ddd 26 p digital power supply lckp 27 i lvds positive data clock input lckn 28 i lvds negative data clock input n.c. 29 g not connected ld[7]p 30 i lvds positive input bit 7 [2] ld[7]n 31 i lvds negative input bit 7 [2] ld[6]p 32 i lvds positive input bit 6 [2] ld[6]n 33 i lvds negative input bit 6 [2] ld[5]p 34 i lvds positive input bit 5 [2] ld[5]n 35 i lvds negative input bit 5 [2] v ddd 36 p digital power supply ld[4]p 37 i lvds positive input bit 4 [2] ld[4]n 38 i lvds negative input bit 4 [2] ld[3]p 39 i lvds positive input bit 3 [2] ld[3]n 40 i lvds negative input bit 3 [2] ld[2]p 41 i lvds positive input bit 2 [2] ld[2]n 42 i lvds negative input bit 2 [2] v ddd 43 p digital power supply ld[1]p 44 i lvds positive input bit 1 [2] ld[1]n 45 i lvds negative input bit 1 [2] ld[0]p 46 i lvds positive input bit 0 [2] ld[0]n 47 i lvds negative input bit 0 [2] io1 48 io io port bit 1 io0 49 io io port bit 0 sdo 50 o spi data output table 2. pin description ?continued symbol pin type [1] description dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 6 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating [1] p: power supply; g: ground; i: input; o: output. [2] the lvds input data bus order can be reversed and each element can be swapped between p and n using dedicated registers (see table 60). sdio 51 io spi data input/output sclk 52 i spi clock scs_n 53 i spi chip select (active low) reset_n 54 i general reset (active low) v dda(1v8)_d 55 p 1.8 v analog power supply (dac core) ioutbn 56 o complementary dac b output current ioutbp 57 o dac b output current v dda(1v8)_d 58 p 1.8 v analog power supply (dac core) v dda(3v3) 59 p 3.3 v analog power supply auxbp 60 o auxiliary dac b output current auxbn 61 o complementary auxiliary dac b output current v dda(1v8)_p1 62 p 1.8 v analog power supply (pll) vires 63 io dac biasing resistor gapout 64 io band gap input/output voltage v dda(1v8)_p2 65 p 1.8 v analog power supply (pll) auxan 66 o complementary auxiliary dac a output current auxap 67 o auxiliary dac a output current v dda(3v3) 68 p 3.3 v analog power supply v dda1v8_d 69 p 1.8 v analog power supply (dac core) ioutap 70 o dac a output current ioutan 71 o complementary dac a output current v dda(1v8)_d 72 p 1.8 v analog power supply (dac core) gnd h g ground (exposed die pad) table 2. pin description ?continued symbol pin type [1] description dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 7 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 7. limiting values [1] connect the analog 1.8 v power supply to pins vdda1v8_d, vdda1v8_p1, and vdda1v8_p2. 8. thermal characteristics [1] value for six-layer board in still ai r with a minimum of 49 thermal vias. table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v ddd digital supply voltage ? 0.5 +2.5 v v dda(1v8) analog supply voltage (1.8 v) [1] ? 0.5 +2.5 v v i input voltage input pins referenced to gnd ? 0.5 +2.5 v v o output voltage pins ioutap, ioutan, ioutbp, ioutbn, auxap, auxan, auxbp and auxbn referenced to gnd ? 0.5 +4.6 v t stg storage temperature ? 55 +150 ? c t amb ambient temperature ? 40 +85 ? c t j junction temperature ? 40 +125 ? c table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient [1] 16.2 k/w r th(j-c) thermal resistance from junction to case [1] 6.7 k/w dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 8 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 9. characteristics table 5. characteristics v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 29; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit v dda(3v3) analog supply voltage (3.3 v) c 3.15 3.3 3.45 v v ddd digital supply voltage c 1.7 1.8 1.9 v v dda(1v8) analog supply voltage (1.8 v) c [2] 1.7 1.8 1.9 v i dda(3v3) analog supply current (3.3 v) auxiliary dac on c 51 55 59 ma i ddd digital supply current (1.8 v) f s = 983.04 67; ? 4 interpolation; no nco; mds off c 475 525 585 ma f s = 620 msps; ? 2 interpolation; nco on; no mds c 400 450 500 ma i dda(1v8) analog supply current (1.8 v) f s = 983.04 msps; 1 v (p-p) c [2] 207 218 230 ma f s = 620 msps; 1 v (p-p) c 207 218 230 ma p tot total power dissipation f s = 983.04 msps; ? 4 interpolation; nco off; mds off c - 1580 - mw f s = 983.04 msps; ? 4 interpolation; 5-bit nco; mds off c - 1500 - mw f s = 620 msps; ? 2 interpolation; 5-bit nco; mds off -1370-mw power-down using spi register c- 63 - mw clock inputs (pins clkp, clkn) v i(clk)dif differential clock input voltage peak-to-peak c 150 - 1000 mv r i input resistance d - 200 - k ? c i input capacitance d- 1 - pf digital inputs (pins ld[15]p to ld[0]p, ld[15]n to ld[0]n, lckp and l ckn, alignp and alignn) v i input voltage ? v gpd ? < 50 mv [3] c 825 - 1575 mv v idth input differential threshold voltage ? v gpd ? < 50 mv [3] c ? 100 - +100 mv r i input resistance d - 100 - ? c i input capacitance d- 0.8 - pf pins lckp and lckn d - 0.9 - pf dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 9 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating digital inputs/outputs (pins mdsn, mdsp) v o(dif)(p-p) peak-to-peak differential output voltage c- 500 - mv c i input capacitance between gnd and pin mdsn or mdsp d- 0.6 - pf r i input resistance d - 100 - ? v i input voltage ? v gpd ? < 50 mv [3] c 825 - 1575 mv v idth input differential threshold voltage ? v gpd ? < 50 mv [3] c ? 100 - +100 mv digital inputs/outputs (pins sdo, sd io, sclk, scs_n, reset_n, io0, io1) v il low-level input voltage cgnd - 0.3v ddd(1v8) v v ih high-level input voltage c0.7v ddd(1v8) -v ddd(1v8) v v ol low-level output voltage pins io0, io1, sdo and sdio cgnd - 0.1v ddd(1v8) v v oh high-level output voltage pins io0, io1, sdo and sdio c0.9v ddd(1v8) -v ddd(1v8) v i il low-level input current maximum vil i ? 10 - +10 ? a i ih high-level input current maximum vil i ? 10 - +10 ? a c i input capacitance d- 2.2 - pf analog outputs (pins iout ap, ioutan, ioutbp, ioutbn) i bias bias current dc current d - 2.5 - ma i o(fs) full-scale output current controlled by the analog gain registers (see table 32) d8.1 - 34 ma default value d - 20 - ma v o output voltage compliance range d 2.3 - v dda(3v3) v v o(cm) common-mode output voltage 1 v (p-p) dac output d - 3 - v 2 v (p-p) dac output - 2.8 - v r o output resistance d- 250 - k ? c o output capacitance between pins outan and outbn and pins outbn and outbp d- 5 - pf ? e o offset error variation d- dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 10 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating ? e g gain error variation d- dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 11 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating t su set-up time manual tuning mode (see figure 16); depends on ldclk_del[3:0] 0000 c ? 300 - - ps 0001 c ? 365 - - ps 0010 c ? 440 - - ps 0011 c ? 520 - - ps 0100 c ? 590 - - ps 0101 c ? 675 - - ps 0110 c ? 750 - - ps 0111 c ? 830 - - ps 1000 c ? 845 - - ps 1001 c ? 845 - - ps 1010 c ? 1000 - - ps 1011 c ? 1100 - - ps 1100 c ? 1220 - - ps 1101 c ? 1290 - - ps 1110 c ? 1360 - - ps 1111 c ? 1450 - - ps t hold hold time manual tuning mode (see figure 15); depends on ldclk_del[3:0]: 0000 c 790 - - ps 0001 c 870 - - ps 0010 c 950 - - ps 0011 c 1055 - - ps 0100 c 1140 - - ps 0101 c 1230 - - ps 0110 c 1360 - - ps 0111 c 1460 - - ps 1000 c 1900 - - ps 1001 c 2075 - - ps 1010 c 2250 - - ps 1011 c 2400 - - ps 1100 c 2560 - - ps 1101 c 2740 - - ps 1110 c 2900 - - ps 1111 c 3000 - - ps table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 29; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 12 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating dac output timing f s(max) sampling rate c 1000 - - msps t s settling time to ?? 0.5 lsb d - 20 - ns internal pll timing f s sampling rate d 50 - 1000 msps 40-bit nco frequency range; f s = 1000 msps f nco nco frequency two?s complement coding register value = 8000000000h d- ? 500 - mhz register value = ffffffffffh d- ? 0.9095 - mhz register value = 0000000000h d- 0 - hz register value = 0000000001h d - +0.9095 - mhz register value = 7fffffffffh d - +499.99909 - mhz f step step frequency d - 0.9095 - mhz low-power nco frequency range; f s = 1000 mhz f nco nco frequency two?s complement coding register value = f8000000000h d- ? 500 - mhz register value = f8000000000h d- ? 31.25 - mhz register value = 00000000000h d- 0 - hz register value = 08000000000h d - +31.25 - mhz register value = 7fffffffffh d - +468.75 - mhz f step step frequency d - 31.25 - mhz dynamic performance sfdr spurious-free dynamic range f data = 245.76 mhz; f s = 983.04 msps; bw = f s /2 f o =20mhz at ? 1dbfs i - 78 - dbc f data = 184.32 mhz; f s = 737.28 msps; bw = f s /2 f o =20mhz at ? 1 dbfs - 78 - dbc table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 29; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 13 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating [1] d = guaranteed by design; c = guaranteed by c haracterization; i = 100 % industrially tested. [2] connect v dda(1v8)_d , v dda(1v8)_p1 and v dda(1v8)_p2 to the same 1.8 v analog power supply. use dedicated filters for the three power pins. [3] ? v gpd ? represents the ground potential difference voltage. this voltage is the result of current flowing through the finite resistanc e and the inductance between the receiver and the driver circuit ground voltages. sfdr rbw restricted bandwidth spurious-free dynamic range f data = 245.76 mhz; f s = 983.04 msps; f o =150mhz --dbc bw = 100 mhz - 78 - dbc bw = 180 mhz - 78 - dbc imd3 third-order intermodulation distortion f data = 245.76 mhz; f s = 983.04 msps; f o1 =20mhz; f o2 =21mhz; ? 4 interpolation; output level = ? 1dbfs c- 75 - dbc f data = 245.76 mhz; f s = 983.04 msps; f o1 = 152 mhz; f o2 = 155.1 mhz; ? ? 4 interpolation; output level = ? 1dbfs i- 75 - dbc acpr adjacent channel power ratio wcdma pattern; f s = 983.04 msps; ? 4 interpolation; f nco =153.6mhz 1 carrier; bw = 5 mhz c - 73 - dbc 2 carriers; bw = 10 mhz c - 70 - dbc 4 carriers; bw = 20 mhz c - 68 - dbc nsd noise spectral density f s = 983.04 msps; ? 4 interpolation; f o =20mhzat ? 1dbfs d- ? 158 - dbm/hz f s = 983.04 msps; ? 4 interpolation; f o =153.6mhzat ? 1dbfs d- ? 155 - dbm/hz table 5. characteristics ?continued v dda(1v8) =1.8v; v ddd =1.8v; v dda(3v3) = 3.3 v; typical values measured at t amb =+25 ? c; r l =50 ? ; i o(fs) =20ma; maximum sample rate used; external pll; no auxiliary dac; no inverse sinus x/x; no output correction; output load condition defined in figure 29; output level = 1 v (p-p). symbol parameter conditions test [1] min typ max unit dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 14 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10. application information 10.1 general description the dac1617d1g0 is a dual 16-bit dac operating up to 1000 msps. each dac consists of a segmented architecture, comprising a 6-bit thermometer subdac and a 10-bit binary weighted subdac. a maximum input lvds ddr data rate of up to 370 mhz and a maximum output sampling rate of 1000 msps ensure more flexibility fo r wide bandwidth and mu lti-carrier systems. the internal 40-bit nco of the dac1617d1g0 simplifies the frequency selection of the system. the dac1617d1g0 provides ? 2, ? 4 or ? 8 interpolation filters that are useful for removing the undesired images. each dac generates two complementary current outputs on pins ioutap and ioutan and pins ioutbp and ioutbn. these outputs provide a full-scale output current (i o(fs) ) of up to 34 ma. an internal reference is available for the reference current which is externally adjustable using pin vires. high resolution internal gain, phase and offset control provide outstanding image and local oscillator (lo) signa l rejection at the system analog modulator output. multiple device synchronization enables synchronization of the outputs of multiple dac devices. mds guarantees a maximum skew of one output clock period between several devices. all functions can be set using an spi interface. 10.2 serial periphera l interface (spi) 10.2.1 protocol description the dac1617d1g0 serial interface is a synch ronous serial communication port ensures easy interface with many industry microprocessors. it provides access to the registers that define the operating modes of the chip in both write and read mode. this interface can be configured as a 3-wire type (pin sdio as bidirectional pin) or 4-wire type (pins sdio and sdo as unidirectional pins , input and output port, respectively). in both configurations, sclk acts as the serial clock and scs_n as the serial chip select. figure 3 shows the spi protocol. an scs_n si gnal follows each read/write operation. a low assertion enables it to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte (see table 7). dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 15 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating r/w indicates the mode access (see table 6) table 7 shows the number of bytes to be transferred. n1 and n0 indicate the number of bytes transferred after the instruction byte. a[4:0] indicates which register is being ad dressed. if a multiple transfer occurs, this address concerns the first register. the other registers follow directly in a decreasing order (see table 21, table 35 and table 53). the dac1617d1g0 incorporates more than the 32 spi registers allowed by the address value a[4:0]. it uses three spi register pages (page_00, page_01, and page_0a), each containing 32 registers. the 32 nd register of each page indicates which page is currently addressed (00h, 01h or 0ah). fig 3. spi protocol 001aan829 reset_n (optional) scs_n sclk sdio sdo (optional) r/w n1 n0 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 table 6. read or write mode access description r/w description 0 write mode operation 1 read mode operation table 7. number of bytes transferred n1 n0 number of bytes transferred 0 0 1 byte 0 1 2 bytes 1 0 3 bytes 1 1 4 bytes dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 16 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.2.2 spi timing description the spi interface can operate at a frequency up to 15 mhz. the spi timings are shown in figure 4. the spi timing characteristics are given in table 8. 10.3 power-on sequence there are three steps for the power-on sequence (see figure 5): 1. the board is power-on. at the turn-on ti me, all dac1617d1g0 supplies have reached their specification ranges. 2. at least 1 ? s after the turn-on time pin reset_n must be released. 3. when the dac clock and lvds clock are stable, the spi configuration is sent to the dac1617d1g0. writing 0 in bits rst_ dclk and rst_lclk of the register main_cntrl (see table 54) starts the automatic calibration. 30 ? s after this calibration, the dac1617d1g0 is operational. fig 4. spi timing diagram table 8. spi timing characteristics symbol parameter min typ max unit f sclk sclk frequency - - 25 mhz t w(sclk) sclk pulse width 30 - - ns t su(scs_n) scs_n set-up time 20 - - ns t h(scs_n) scs_n hold time 20 - - ns t su(sdio) sdio set-up time 10 - - ns t h(sdio) sdio hold time 5 - - ns t w(reset_n) reset_n pulse width 30 - - ns 001aan830 50 % t w(reset_n) t su(scs_n) t su(sdio) t h(sdio) t h(scs_n) t w(sclk) 50 % reset_n (optional) scs_n sclk sdio 50 % 50 % dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 17 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.4 lvds data input format (dif) block the data input formatting (dif) block captures and resynchronizes data on the lvds bus with its own lclkp/lclkn clock. each lvds input buffer has an internal resistance of 100 ? , so an external resistor is not required. the dif block includes two subblocks: ? lvds receiver: provides high flexibility for the lvds interf ace, especially for th e pcb layout and the control of the input port polarity and the input port mapping. ? data format block: enables the adaptation, which ensures the support of several data encoding modes. 10.4.1 input port polarity the polarity of each individual lvds input (ld[15]p to ld[0]p and ld[15]n to ld[0]n) can be changed. this ensures a much easier pcb layout design. the input polarity is controlled with bits ld_pol[15:0] (see table 59). 10.4.2 input port mapping inverting the order of the lsb and the msb of the lvds bus using bit word_swap in register ld_cntrl (see table 60) also simp lifies the design of the pcb (see table 9). fig 5. power-on sequence 001aan810 spi bus write dac configuration start clock calibration time reset_n t on power in specification range t spi_start t rst power supplies fig 6. lvds data input format (dif) block diagram 16 16 001aan392 lvds receiver to dac a to dac b pa[15..0] pb[15..0] 16 16 i[15..0] q[15..0] lclk ld[15]p ld[15]n ld[0]p ld[0]n lclkp lclkn data format dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 18 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.4.3 input port swapping the lvds ddr receiver block internally ma ps the incoming lvds data bus into two buses with a single data rate (figure 7). these two buses can be swapped internally using bit ldab_swap of register ld_cntrl (see table 60 and figure 8). table 9. input lvds bus swapping internal lvds bus external lvds bus (word_swap = 0) external lvds bus (word_swap = 1) ldi[15]p,n ld[15]p,n ld[0]p,n ldi[14]p,n ld[14]p,n ld[1]p,n ldi[13]p,n ld[13]p,n ld[2]p,n ldi[12]p,n ld[12]p,n ld[3]p,n ldi[11]p,n ld[11]p,n ld[4]p,n ldi[10]p,n ld[10]p,n ld[5]p,n ldi[9]p,n ld[9]p,n ld[6]p,n ldi[8]p,n ld[8]p,n ld[7]p,n ldi[7]p,n ld[7]p,n ld[8]p,n ldi[6]p,n ld[6]p,n ld[9]p,n ldi[5]p,n ld[5]p,n ld[10]p,n ldi[4]p,n ld[4]p,n ld[11]p,n ldi[3]p,n ld[3]p,n ld[12]p,n ldi[2]p,n ld[2]p,n ld[13]p,n ldi[1]p,n ld[1]p,n ld[14]p,n ldi[0]p,n ld[0]p,n ld[15]p,n fig 7. lvds ddr receiver mapping ldab swap = 0 001aan393 a0 b0 a1 b1 a2 b2 a3 b3 lvds receiver ld[15..0]p/n lclkp/n pa[15..0] pb[15..0] lclk a0 a1 to dac a to dac b a2 a3 b0 b1 b2 b3 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 19 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.4.4 input port formatting the lvds ddr input bus multiplexes two 16 -bit streams. the lvds receiver block demultiplexes these two streams. the two streams can carry two data formats: ? folded ? interleaved the data format block is in charge of t he data format adaptation (see figure 9). the dac1617d1g0 can correctly decode the input stream using bit iq_format of register ld_cntrl (see table 60), because it can determine which format is used on the lvds ddr bus. table 10 shows the format mapping between the lvds input data and the data sent to the two dac channels depending on the data format selected. fig 8. lvds ddr receiver mapping ldab swap = 1 001aan394 a0 b0 a1 b1 a2 b2 a3 b3 lvds receiver ld[15..0]p/n lclkp/n pa[15..0] pb[15..0] lclk b0 b1 to dac a to dac b b2 b3 a0 a1 a2 a3 fig 9. lvds ddr data formats 001aan395 a0 b0 a1 b1 a2 b2 a3 b3 lvds receiver ld[15..0]p/n lclkp/n pa[15..0] pb[15..0] lclk data format a0 a1 a2 a3 b0 b1 b2 b3 i0 i1 to dac a to dac b i2 i3 q0 q1 q2 q3 table 10. folded and interleaved format mapping data format data bit mapping interleaved format (iq_format = 1) in[15. .0] = an[15..0]; qn [15..0] = bn[15..0] folded format (iq_format = 0) in[15..8 ] = an[15..8]; in [7..0] = bn[15..8] qn[15..8] = an[7..0]; qn[7..0] = bn[7..0] dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 20 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.4.5 data parity/data enable the align pins can be used in several ways: ? as datastream start flag for multiple devices synchronization (see section 10.13). ? as lvds data enable which can be used to insert a dc level into the datastream. the sel_en bits in register ld_cntrl (see table 60) enable the programming of this mode. the dc level for both channels is selected using registers i_dc_lvl and q_dc_lvl (see table 62) ? as parity bit for the ld[15:0] to detect di sruptions at the lvds-input port bit parityc in register ld_cntrl (see table 60) enabling the control of this mode. a parity error can generate an interrupt (intr) reported on either io0 or io1 pin 10.5 interrupt controller the dac1617d1g0 incorporates an interrupt controller that makes notifying a host-controller in case of an internal event. the intr-signal can be made available on one of the io pins. the polarity on the io pins is programmable. the internal event that must be tracked and generates an interrupt can be selected using the intr_en register (see table 45). two types of interrupt sources are considered: ? the ready-indicators (maq_rdy_b, maq_rdy_a, auto_cal_rdy, and auto_dl_rdy; register intr_flags; see tabl e table 47) notify the host-interface that the corresponding process (invoked by the host interface) has been finalized ? the error flags indicate that a failure has been detected. for example, on the lvds-interface it is possible to check for pari ty errors and/or to monitor if the internal timing of the lvds clock delay has changed since the calibration. errors like these can result in critical timings within the clock domain interface (cdi) which transfers the data from the lclk to the dclk domain the selected event that has invoked the interrupt can be determined using the intr_flags register (see table 47). the flag s and the intr signal are reinitialized by setting the intr_clear control bit in register intr_ctrl (see table 45). 10.6 general-purpose io pins the dac1617d1g0 provides two general-purpo se pins, io0 and io1. these pins can be used to observe the interrupt signal (intr) or other internal signals (internal clocks, lvds data, etc.). these pins can also be used as generic outputs to control external devices. the internal signals that must be observed on these pins are selected using registers io_mux0, io_mux1, and io_mux2 (see table 63 and table 64). 10.7 input clock the dac1617d1g0 operates with two clocks, one for the lvds ddr interface and one for the dac core. 10.7.1 lvds ddr clock the lvds ddr clock can be interfaced as sh own in figure 10 because the clock buffer contains a 100 ? internal resistor. dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 21 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.7.2 dac core clock the dac core clock can achieve a frequency of up to 1 gsps. it includes internal biasing to support both ac-coupling and dc-coupling. the clock can be easily connected to any lvds, cml or pecl clock sources. depending on the interface selected, the hardware configuration varies (see figure 11 to figure 13). fig 10. lvds ddr clock configuration d d d y ' $ & ' / 9 ' 6 / & / . 3 / & / . 1 / 9 ' 6 a. dc-coupling b. ac-coupling fig 11. dac core clock: lvds configuration d d d y / 9 ' 6 & / . 3 & / . 1 ' $ & ' d d d y / 9 ' 6 & / . 3 & / . 1 ' $ & ' q ) q ) dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 22 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.8 timing the dac1617d1g0 can operate at an update rate (f s ) of up to 1 gsps and with an input data rate (f data ) of up to 370 mhz. the sampling position of the lvds data can be tuned using a 16-step compensation delay clock. an internal clock is generated to define the exact sampling position of the lvds data (see figure 14, signals ldclkpcp and ldclkncp) which depends on the compensation delay. figure 14 shows how the compensation delay helps to recover th e lvds ddr data on both the a and b paths. fig 12. dac core clock: cml configuration with ac-coupling fig 13. dac core clock: pecl configuration with ac-coupling d d d y ' $ & ' y & 0 / 9 9 & / . 3 & / . 1 q ) q ) d d d y ' $ & ' y 3 ( & / & / . 3 & / . 1 q ) q ) dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 23 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating the compensation delay time (t cmp in figure 14) can be tuned automatically or manually. bit cal_cntrl of the main_cntrl register (see table 54) enables the switching between automatic tuning and manual tuning. in automatic tuning mode, the external lvds data and clock signals are generated using the same reference clock (inside the fpga). the ldclk clock is similar to a data bit that toggles each time (the rising ed ge and falling edge of the ldclk and lvds data occur at the same time). in automatic tuning, th e internal compensation delay time (t cmp ) is defined automatically to compensate the internal dac1617d1g0 delay time optimally. the timing requirement in automatic tuning mode is defined in figure 15 and in table 5. fig 14. lvds ddr demux timing (lvds a an d b paths not swapped; ldab_swap = 0) t sk(min) = minimum skew time t sk(max) = maximum skew time fig 15. timing requirem ent automatic tuning 001aan400 d n [i] d n [i] d n + 1 [i] d n + 1 [i] d n + 3 [i] d n ? 1 [i] t cmp d n ? 1 [i] d n + 2 [i] d n + 2 [i] ldclkn ldclkp ld[i]n ld[i]p ldclkncp ldclkpcp lda[i] ldb[i] 001aan833 lvds data lvds clock v ih v il v ih v il t sk(min) t sk(max) dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 24 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating use manual tuning mode if the lvds data and the ldclk clock signals provided to the dac1617d1g0 device have a systematic delay. the compensation delay time can be adjusted to compensate for the systematic delay. the compensation delay time (t cmp in figure 14), can be defined using bits ldcl k_del[3:0] of register man_ldclkdel (see table 55). the timing requirement in manual tuning mode is defined in figure 16 and in table 5. 10.9 operating modes the dac1617d1g0 requires two differential clocks: ? the lvds clock (ldclkp, ldclkn) for the lvds ddr interface ? the data clock (clkp, clkn) for the internal pll and the dual dac core in normal mode, provide both the dac cloc k and the lvds clock to the dac1617d1g0. align the ratio frequency between th ese two clocks needs with selected ? 2, ? 4 or ? 8 interpolation filters. the clocks provided to the dac1617d1g0 must respect the lvds input timing and the dac output timing sp ecifications as defined in table 5. in pll mode, provide the lvds clock to pins ldclkp/ldclkn and pins clkp/clkn. depending on selected interpolation filter, the internal pll can be set to generate the right dac core clock frequency internally. the clo cks provided to the dac1617d1g0 pins must respect the lvds input timing and the dac out put timing specifications as defined in table 5. the pll settings must also respect the maximum sampling rate of the pll (see the sampling rate (f s ) in subsection internal pll timing of table 5). the main function of the clock domain interf ace (cdi) is to resynchronize the input data streams to the internal clock the digital processing uses. the cdi also performs the required reformatting of the input datastreams. set pll, cdi, and the interpolation filters, which depend on the targeted application accordingly. section 10.9.1 ( ? 2), section 10.9.2 ( ? 4), and section 10.9.3 ( ? 8) explain how to set the dac1617d1g0 to support the different upsampling modes. fig 16. timing requirement in manual tuning mode / 9 ' 6 g d w d w v x q h j d w l y h / ' & / . v d p s o l q j z l q g r z v d p s o l q j z l q g r z w k r o g d d d dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 25 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.9.1 cdi mode 0 (x2 interpolation) cdi mode 0 ( ? 2 interpolation) is requir ed when the value of the lvds ddr clock is twice the internal maximum cdi frequency. table 11 shows examples of applications using an internal pll or an external clock for the dac core. [1] bits cdi_mode[1:0] of register misc_cntrl (see table 61). [2] bits interpolation[1:0] of register txcfg (see table 23). [3] if a single sideband modulator (ssbm) is used, see bits nco _on and modulation[2:0] of register txcfg (see table 23). [4] pins clkp and clkn (see figure 2). [5] bit pll_pd of register pllcfg (see table 24). [6] bits pll_div[1:0] of register pllcfg (see table 24). 10.9.2 cdi mode 1 (x4 interpolation) cdi mode 1 ( ? 4 interpolation) is required when the values of the lvds ddr clock and the internal cdi frequency are equal. table 12 shows examples of applications using an internal pll or an external clock for the dac core. [1] bits cdi_mode[1:0] of register misc_cntrl (see table 61). [2] bits interpolation[1:0] of register txcfg (see table 23). [3] if ssbm is used, see bits nco_on and modulatio n[2:0] of register txcfg (see table 23). [4] pins clkp and clkn (see figure 2). [5] bit pll_pd of register pllcfg (see table 24). [6] bits pll_div[1:0] of register pllcfg (see table 24). table 11. cdi mode 0: operating modes examples lvds ddr rate (mhz) i rate; q rate (msps) cdi mode [1] fir mode [2] ssbm rate [3] (msps) dac rate (msps) pll configuration dac input clock [4] (mhz) pll status [5] pll divider [6] 320 320 0 ? 2 640 640 320 enabled 2 320 320 0 ? 2 640 640 640 disabled n.a. table 12. cdi mode 1: operating modes examples lvds ddr rate (mhz) i rate; q rate (msps) cdi mode [1] fir mode [2] ssbm rate [3] (msps) dac rate (msps) pll configuration dac input clock [4] (mhz) pll status [5] pll divider [6] 250 250 1 ? 4 1000 1000 250 enabled 4 250 250 1 ? 4 1000 1000 1000 disabled n.a. dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 26 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.9.3 cdi mode 2 (x8 interpolation) cdi mode 2 ( ? 8 interpolation) is required when the lvds ddr clock is half the maximum cdi frequency or less. table 13 shows examples of applications using an internal pll or an external clock for the dac core. [1] bits cdi_mode[1:0] of register misc_cntrl (see table 61). [2] bits interpolation[1:0] of register txcfg (see table 23). [3] if ssbm is used, see bits nco_on and modulatio n[2:0] of register txcfg (see table 23). [4] pins clkp and clkn (see figure 2). [5] bit pll_pd of register pllcfg (see table 24). [6] bits pll_div[1:0] of register pllcfg (see table 24). 10.10 fir filters the dac1617d1g0 integrates three selectable finite impulse response (fir) filters which enable the use of the device with ? 2, ? 4 or ? 8 interpolation rates. all three interpolation fir filters have a stop-band attenuation of at least 80 dbc and a pass-band ripple of less than 0.0005 db. table 14 shows the coefficients of the interpolation filters. table 13. cdi mode 2: operating modes examples lvds ddr rate (mhz) i rate; q rate (msps) cdi mode [1] fir mode [2] ssbm rate [3] (msps) dac rate (msps) pll configuration dac input clock [4] (mhz) pll status [5] pll divider [6] 125 125 2 ? 8 1000 1000 125 enabled 4 125 125 2 ? 8 1000 1000 1000 disabled n.a. fig 17. first stage half-band filter response nf (fs) 0 0.5 0.4 0.2 0.3 0.1 001aao039 magnitude (db) 0 -100 -20 -40 -80 -60 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 27 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating fig 18. second stage half-band filter response fig 19. third stage half-band filter response table 14: interpolation filter coefficients first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value - h(27) +65536 h(11) - +32768 h(7) - +1024 h(26) h(28) +41501 h(10) h(12) +20272 h(6) h(8) +615 h(25) h(29) 0 h(9) h(13) 0 h(5) h(9) 0 h(24) h(30) ? 13258 h(8) h(14) ? 5358 h(4) h(10) ? 127 h(23) h(31) 0 h(7) h(15) 0 h(3) h(11) 0 h(22) h(32) +7302 h(6) h(16) +1986 h(2) h(12) +27 h(21) h(33) 0 h(5) h(17) 0 h(1) h(13) 0 h(20) h(34) ? 4580 h(4) h(18) ? 654 h(0) h(14) ? 3 nf (fs) 0 0.5 0.4 0.2 0.3 0.1 001aao040 magnitude (db) 0 -100 -20 -40 -80 -60 nf (fs) 0 0.5 0.4 0.2 0.3 0.1 001aao041 magnitude (db) 0 -100 -20 -40 -80 -60 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 28 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating equation 1 defines the dependency of the fir1 output y(m) on its inputs x(m): (1) equation 2 defines the dependency of the fir2 output y(m) on its inputs x(m): (2) equation 3 defines the dependency of the fir3 output y(m) on its inputs x(m): (3) h(19) h(35) 0 h(3) h(19) 0 - - - h(18) h(36) +2987 h(2) h(20) +159 - - - h(17) h(37) 0 h(1) h(21) 0 - - - h(16) h(38) ? 1951 h(0) h(22) ? 21 - - - h(15)h(39)0------ h(14) h(40) +1250 - - - - - - h(13)h(41)0------ h(12)h(42)-773------ h(11)h(43)0------ h(10) h(44) +456 - - - - - - h(9) h(45) 0 - - - - - - h(8) h(46) ? 252------ h(7) h(47) 0 - - - - - - h(6) h(48) +128 - - - - - - h(5) h(49) 0 - - - - - - h(4) h(50) ? 58------ h(3) h(51) 0 - - - - - - h(2) h(52) +22 - - - - - - h(1) h(53) 0 - - - - - - h(0) h(54) ? 6------ table 14: interpolation filter coefficients ?continued first interpolation filter second interpolation filter third interpolation filter lower upper value lower upper value lower upper value ym ?? 1 h27 ?? --------------- hn ?? : xm n ? ?? ?? n0 = n54 = ? ? = ym ?? 1 h11 ?? --------------- hn ?? : xm n ? ?? ?? n0 = n22 = ? ? = ym ?? 1 h7 ?? ------------ hn ?? : xm n ? ?? ?? n0 = n14 = ? ? = dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 29 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.11 single sideband modulator (ssbm) the ssbm is a quadrature modulator that enables mixing the i data and q data with the sine and cosine signals generated by the nco to generate path a and path b (see figure 20). the frequency of the nco is programmed over 40 bits. nco enables inverting the sine component to operate a positive or ne gative, lower or upper ssb upconversion (see register txcfg in table 23). 10.11.1 nco in 40 bits when using nco, the frequency can be set over 40 bits by five registers, freqnco_b0 to freqnco_b4 (see table 25). the frequency is calculated with equation 4. (4) where: ? m is the two?s complement coding representation of freq_nco[39:0] ? f s is the dac clock sampling frequency the default settings are: ? f nco =96mhz ? f s =640msps registers phinco_lsb and phin co_msb over 16 bits from 0 ? to 360 ? (see table 31) can set the phase of the nco. fig 20. ssbm principle 001aan575 +/ ? cos a b i sin +/ ? sin q cos +/ ? f nco mf s ? 2 40 -------------- = dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 30 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.11.2 nco low power the five msb-bits of register freqnco_b4 (bits freq_nco[39:35]; see table 25) can set the frequency, when using nco low power (bit nco_lp_sel; see table 23). the frequency is calculated with equation 5. (5) where: ? m is the two?s complement coding representation of freq_nco[39:35] ? f s is the dac clock sampling frequency the five msb-bits of register phinco_msb (s ee table 31) can set the phase of the nco low power. 10.11.3 complex modulator the complex modulator upconverts the single side band by mixing nco signals and i and q input signals. table 15 shows the various po ssibilities set by bits modulation[2:0] of register txcfg (see table 23). the effect of the modulation parameter is better viewed after mixing the a and b signal with a lo frequency through an iq modulator: f nco mf s ? 2 5 -------------- = fig 21. complex modulation after lo mixing / 2 1 & 2 q h j d w l y h s r v l w l y h o r z h u x s s h u o r z h u x s s h u / 2 1 & 2 / 2 i u h t x h q f \ d d d table 15. complex modulator operation mode modulation[2:0] mode path a path b 000 bypass 001 positive upper sob 010 positive lower ssb 011 negative upper ssb 100 negative lower ssb others not defined - - it ?? qt ?? it ?? ? nco t ? ?? cos q t ?? ? nco t ? ?? sin ? ? ? it ?? ? nco t ? ?? sin q t ?? ? nco t ? ?? cos ? + ? it ?? ? nco t ? ?? cos q t ?? ? nco t ? ?? sin ? + ? it ?? ? nco t ? ?? sin q t ?? ? nco t ? ?? cos ? ? ? it ?? ? nco t ? ?? cos q t ?? ? nco t ? ?? sin ? ? ? it ?? ? ? nco t ? ?? sin q t ?? ? nco t ? ?? cos ? ? ? it ?? ? nco t ? ?? cos q t ?? ? nco t ? ?? sin ? + ? it ?? ? ? nco t ? ?? sin q t ?? ? nco t ? ?? cos ? + ? dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 31 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.11.4 minus 3db in normal use, a full-scale pattern is also fu ll-scale at the dac out put. nevertheless, when the i data and q data come close to full-scale simultaneously, some clipping can occur. the minus 3db function (bit minus_3db of register dac_out_ctrl; see table 28) can be used to reduce the 3 db gain in the modulator. it retains a full-scale range at the dac output without added interferers. 10.12 inverse (sin x) / x a selectable fir filter is inco rporated to compensate the (sin x) / x effect caused by the roll-off effect of the dac. this filter has no effect at dc. it introduces a gain for high frequency. the coefficients are represented in table 16. the filter response is presented in figure 22. 10.13 multiple devices sy nchronization (mds) several dac channels can be sampled sync hronously and phase coherently using the mds feature. when all dac slave devices of one system re ceive the same mds signal (or at least a synchronous version of this reference) all devices are time-aligned at ? 1 dac clock accuracy at the end of the synchronization process. table 16. inversion filter coefficients first interpolation filter lower upper value h(1) h(9) +1 h(2) h(8) ? 4 h(3) h(7) +13 h(4) h(6) ? 51 h(5) - +610 fig 22. inverse (sin x) / x response 1 r u p d o l ] h g ) u h t x h q f \ [ i r x w i v d d d 0 d j q l w x g h g % dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 32 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.13.1 mds concept the fpga(s) has(have) to activate the align pi ns to identify the lvds data flow start (see figure 23). the align signal is used to generate a lo cal reference inside the dac1617d1g0 which is 'aligned' with the iq-data. the dac1617d1g0 devices use the mds signals to do the output synchronization (see figure 24). fig 23. align lvds data o q 4 q d o l j q / 9 ' 6 g d w d o q 4 q o q 4 q o q 4 p o p 4 p o p 4 p o p 4 p o p 4 p o p d d d dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 33 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating the signal detector of the dac1617d1g0 detect s the presence of the mds signals. once detected, an internal copy process of this re ference starts. the mds early/late detector block then compares the phase difference of these two signals to align the copy to its reference accurately. the alignment is done in side an "enabling window" that avoids the misinterpretation of the signal edges. this alignment process is done by moving the internal pointer of register mds_adjdelay (see table 43) (so inserting/removing a delay in data flow). this pointer can have a pres et offset. this is specified by register mds_offset_dly (see table 42). usin g the mds_man and mds_man_adjdelay bits in register mds_man_adjustly register (see table 39), the alignment can also be set manually. fig 24. mds synchronization ' $ 7 $ ) / 2 : ' ( / $ < 0 ' 6 & 2 1 7 5 2 / $ 1 ' * ( 1 ( 5 $ 7 , 2 1 0 ' 6 l q w h u q d o u h i ( $ 5 / < / $ 7 ( ' ( 7 ( & 7 2 5 h d u o \ o d w h z l q g r z ' $ & $ ' $ & $ d d d ' $ 7 $ ) / 2 : ' ( / $ < 0 ' 6 & 2 1 7 5 2 / $ 1 ' * ( 1 ( 5 $ 7 , 2 1 0 ' 6 l q w h u q d o u h i ( $ 5 / < / $ 7 ( ' ( 7 ( & 7 2 5 h d u o \ o d w h z l q g r z ' $ & $ ' $ & 6 / $ 9 ( ' $ & 0 $ 6 7 ( 5 ' $ & $ ' $ & & / . 0 ' 6 / 9 ' 6 d o l j q / 9 ' 6 g d w d ' $ & & / . 0 ' 6 / 9 ' 6 d o l j q / 9 ' 6 g d w d d o l j q 0 ' 6 d g m g h o d \ d o l j q 0 ' 6 d g m g h o d \ dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 34 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating during the whole alignment process, the mds controller tries to adjust the delay to get the internal copy signal aligned to the external mds signal. once aligned, the mds signal is not required anymore. it can be switched off at system level. the alignment is done just in front of the analog dacs cores ensuring the ? 1 dac clock sample accuracy. at the end of the mds process, the mds ci rcuitry is disabled to avoid any analog disturbances. the mds feature can be used in two modes: ? all slaves mode ? master/slaves mode the mode can be set using the md_master bit of register mds_main (see table 36). 10.13.1.1 mds in all slaves mode in this mode, each device uses its align pins signal to identify the lvds data flow start (see figure 23). the fpga(s) has(have) to generate these align signals. the fpga is also used to generate the diff erent mds reference signals to enable the dac1617d1g0 devices to do the synchronization of the output. use this mode when two or more dac1617d1g0 devices must be synchronized. figure 25 shows the mds all slave mode schematic. fig 25. mds in all slaves mode ' $ & $ d o l j q / ' > @ / & / . 0 ' 6 w r ' ( 9 q 0 ' 6 d o l j q / ' > @ / & / . ' $ & ' ( 9 , & ( ) 3 * $ 0 ' 6 5 ( ) ( 5 ( 1 & ( * ( 1 ( 5 $ 7 2 5 v \ v w h p v w d u w u h i h u h q f h ) 3 * $ ' $ & % ' $ & $ ' $ & ' ( 9 , & ( & / 2 & . ' , 6 7 5 , % 8 7 , 2 1 ' $ & % d o o r x w s x w d u h d o l j q h g ' $ & & / . u h i w r ) 3 * $ q ' $ & & / . w r g h y l f h q d d d dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 35 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.13.1.2 mds in master/slaves mode in this mode, one dac1617d1g0 device is us ed as master, the other one is used as slave. the fpga(s) still has(ha ve) to provide the align sig nal to the dac devices to identify the lvds data flow start (see fi gure 23). the master generates the reference mds signal. the slave uses this signal to do the synchronization of the output. this mode is recommended when only two dac1617 d1g0 devices must be synchronized. figure 25 shows the mds mast er/slaves mode schematic. 10.13.2 mds flexibility and constraints getting a ? 1 clock period alignment can become very difficult without the mds feature. there are many sources of misalignment: ? at 1 ghz, two signals with only 15 cm pcb length difference have a 1 clock period skew. so the pcb traces off the fpga refe rence clock, the lvds data/clock, or the dac clock introduce delay. ? the clock generation circuit can caus e delay between the different clocks. ? the most important delay comes from the inte rnal fpga design that can cause 1 or 2 lvds clock delays between the different lvds data patterns. the dac1617d1g0 mds feature compensates these delays when: ? the overall delay compensated by the dac1617d1g0 remains below ? 64 dac clock. ? each fpga has to activate its align signal with the beginning of the lvds data flow start (even if the different align signals are mis-aligned) fig 26. mds master/slaves mode ' $ & $ d o l j q / ' > @ / & / . 0 ' 6 l q s x w 0 ' 6 r x w s x w d o l j q / ' > @ / & / . ' $ & 6 / $ 9 ( ' ( 9 , & ( ) 3 * $ v \ v w h p v w d u w u h i h u h q f h ) 3 * $ ' $ & % ' $ & $ ' $ & 0 $ 6 7 ( 5 ' ( 9 , & ( & / 2 & . ' , 6 7 5 , % 8 7 , 2 1 ' $ & % d o o r x w s x w d u h d o l j q h g ' $ & & / . u h i ' $ & & / . d d d dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 36 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating ? all slave devices use the mds signals fo r the fine alignment. any misalignment between these signals causes misalignmen t on the output. minimize the delay between the different mds signals to avoid misalignments: ? in all slave mode: use a low skew buffer on the fpga to generate this signal. use the same pcb length for all md s signal trace distributions. ? in master/slave mode: minimize the mds pcb length between the master and the slave (or compensate the introduced mds pcb delay manually). 10.14 dac transfer function the full-scale output current for each dac is the sum of the two complementary current outputs: ? ? the output current of dac a depends on the digital input data. bits dac_a_dgain[11:0] of register dac_a_dgain_lsb (see table 27) define the gain factor. (6) (7) the output current of dac b depends on the digital input data. bits dac_b_dgain[11:0] of register dac_b_dgain_lsb (see table 27) define the gain factor. (8) (9) it is possible to define if the dac1617d1g0 operates with a binary input or a two's complement input (bit coding; see table 22). table 17 shows the output current as a function of the input data, when i oa(fs) =i ob(fs) =20ma. table 17. dac transfer function data i15 to i0/q15 to q0 (binary coding) i15 to i0/q15 to q0 (two?s complement coding ioutap/ioutbp ioutan/ioutbn 0 0000 0000 0000 0000 1000 0000 0000 0000 0 ma 20 ma ... ... ... ... .... 32768 1000 0000 0000 0000 0000 0000 0000 0000 10 ma 10 ma ... ... ... ... ... 65535 1111 1111 1111 1111 0111 1111 1111 1111 20 ma 0 ma i oa fs ?? i ioutap i ioutan + = i ob fs ? ?? i ioutbp i ioutbn + = i ioutap i oa fs ?? dacadgain ?? 1024 ----------------------------------------- data 65535 --------------- - ?? ?? ? ? = i ioutan i oa fs ?? 1 dacadgain ?? 1024 ----------------------------------------- data 65535 --------------- - ?? ?? ? ? ?? ?? ? = i ioutbp i ob fs ?? dacbdgain ?? 1024 ----------------------------------------- data 65535 --------------- - ?? ?? ? ? = i ioutbn i ob fs ?? 1 dacbdgain ?? 1024 ----------------------------------------- data 65535 --------------- - ?? ?? ? ? ?? ?? ? = dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 37 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.15 full-scale current 10.15.1 regulation the dac1617d1g0 reference circuitry integrates an internal band gap reference voltage which delivers a 1.25 v reference on the g apout pin. decouple pin gapout using a 100 nf capacitor. the reference current is generated via an external resistor of 910 ? (1 %) connected to vires. a control amplifier sets the appropriate full-scale current (i oa(fs) and i ob(fs) ) for both dacs (see figure 27)). figure 27 shows the optimal configuration for temperature drift compensation because the band gap reference voltage can be matched to the voltage across the feedback resistor. applying an external reference voltage to the non-inverting input pin gapout and disabling the internal band gap reference voltage (bit gap_pon of the common register; see table 22) also adjust the dac current. 10.15.2 full-scale current adjustment the default full-scale current (i o(fs) ) is 20 ma. however, further adjustments, ranging from 8.1 ma to 34 ma, can be made to both dacs independently using the serial interface. the settings applied to dac_a_gain[9:0] (registers 17h and 18h; see table 32) define the full-scale current of dac a: (10) the dac_b_gain[9:0] (registers 19h and 1ah; see table 32;) define the full-scale current of dac b: (11) fig 27. internal reference configuration d d d q ) ' $ & & 8 5 5 ( 1 7 6 2 8 5 & ( 6 $ 5 5 $ < % $ 1 ' * $ 3 5 ( ) ( 5 ( 1 & ( * $ 3 2 8 7 $ * 1 ' $ * 1 ' 9 , 5 ( 6 ' $ & ' i ofs ?? ? a ?? 8100 dac_a_gain[9:0] 25.3 ? + = i ofs ?? ? a ?? 8100 dac_b_gain[9:0] 25.3 ? + = dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 38 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.16 limiter/clip control a limiter at the end of the data path saturate s the output signal in case the signal does not fit the output range. this fe ature is activated using the clipping_ena bit in register dac_out_ctrl (see table 28). the clipping level can be programm ed using the clipping_level register (see table 29.). the output range is limited (or clipped) to between ? 128x clipping_level and +128x clipping_level. at the dac analog output, the ac current range is limited to: (12) 10.17 digital offset adjustment the dac1617d1g0 provides digital offset correction (bits dac_a_offset[15:0] in table 30). this correction can be used to adj ust the common-mode level at the output of each dac. it adds an offset at the end of th e digital part, just before the dacs. table 18 shows the range of variation of the digital offset. this offset can be used to remove the lo image at the iq modulator output. 10.18 analog output the device has two output channels, producing two complementary current outputs, which enable the reduction of even-order harmonics and noise. the pins are ioutap/ioutan and ioutbp/ioutbn. connect these pins via a load resistor r l to the 3.3 v analog power supply (v dda(3v3) ). figure 28 shows the equivalent analog output circuit of one dac. this circuit includes a parallel combination of nmos current sources and associated switches for each segment. i ofs ?? 2 -------------- ?? ?? ? clipping _ level 256 --------------------------------------------------- - ?? ?? ? i iout + i ofs ?? 2 -------------- ?? ?? clipping _ level 256 --------------------------------------------------- - ?? ?? ? ?? table 18. digital offset adjustment dac_a_offset[15:0] dac_b_offset[15:0] (two?s complement) offset applied 1000 0000 0000 0000 ? 32768 1000 0000 0000 0001 ? 32767 ... ... 1111 1111 1111 1111 ? 1 0000 0000 0000 0000 0 0000 0000 0000 0001 +1 ... ... 0111 1111 1111 1110 +32766 0111 1111 1111 1111 +32767 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 39 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating the cascode source configuration increases the ou tput impedance of the source, which improves the dynamic performance of the dac because there is less distortion. depending on the application, the various stages and the targeted performances, the device can be used for an output level of up to 2 v (p-p). 10.19 auxiliary dacs the dac1617d1g0 integrates two auxiliary dacs, which are used to compensate any offset between the dacs and the next stage in the transmission path. both auxiliary dacs have a 10-bit resolution and are current sources (referenced to ground). the full-scale output current for each dac is the sum of the two complementary current outputs: ? ? the output current depends on the digital input data set by spi registers dac_a_aux_msb (bits aux_a[9:0]) and dac_b_aux_msb (bit s aux_b[9:0]; see table 33). (13) (14) (15) (16) fig 28. equivalent analog output circuit 001aan835 r l ioutap/ioutbp ioutan/ioutbn 3.3 v gnd gnd r l 3.3 v i oauxa fs ?? i auxap i auxan + = i oauxb fs ?? i auxbp i auxbn + = i auxap i oauxa fs ?? dataa 1023 ------------------- - ?? ?? ? = i auxan i oauxa fs ?? 1023 dataa ? 1023 ------------------------------------- - ?? ?? ? = i auxbp i oauxb fs ?? datab 1023 ------------------- - ?? ?? ? = i auxbn i oauxb fs ?? 1023 datab ? 1023 ------------------------------------- - ?? ?? ? = dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 40 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 19 shows the output curr ent as a function of the au xiliary dacs data dataa and datab in equation 13 to equation 16. 10.20 output c onfiguration the dac1617d1g0 supports various output configurations. the system application must check that fo r iouta/ioutb output, the output compliance range (v o ) and the common-mode output voltage (v o(cm) ) specification points are respected to define other configurations. similarly, the system application must check that the output compliance range (v o ) specification point is respected for auxa/auxb dac (if used). the common-mode voltage (v o(cm) ) value for each iouta/ioutb pin depends on the dc resistor(s) connected to these pins and th e iout dc sink currents on these pins. equation 17 defines the dc sink output current is: (17) where: ? i o(fs) = full-scale output current ? i bias (dc) = dc bias current the common-mode voltage (v o(cm) ) value for each auxa/auxb pins depend on the dc resistor(s) connected to these pins and the aux dc source currents. equation 18 defines these aux dc source currents: (18) where: ? i o(fs) = full-scale output current the output compliance range (v o ) of all dac outputs depends on the ac resistor load connected to the dac: table 19. auxiliary dac transfer function dataa; datab aux_a[9:2]/aux_a[1:0]; aux_b[9:0]/aux_b[1:0] (binary coding) i auxap ; i auxbp (ma) i auxan ; i auxbn (ma) 0 00 0000 0000 0 3.1 ... ... ... ... 512 10 0000 0000 1.55 1.55 ... ... ... ... 1023 11 1111 1111 3.1 0 i ok sin ?? dc ?? i bias dc ?? i ofs ?? 2 ------------ + = i o source ?? dc ?? i ofs ?? 2 ------------ = dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 41 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating (19) (20) where: ? v o(cm) = common-mode output voltage ? i o(fs) = full-scale output current ? r ac = dac outputs ac resistor load 10.20.1 basic output configuration the use of a differentially coupled transfor mer output (see figure 29) provides optimum distortion performance. in a ddition, it helps to match the impedance and provides electrical isolation. the dac1617d1g0 can operate a differential output of up to 2 v (p-p). in this configuration, connect the center tap of the transformer to a 33 ? resistor, which is connected to the 3.3 v analog power supply. this adjusts the dc common-mode to around 2.8 v (see figure 30). v omax ?? v ocm ?? i ofs ?? 2 ------------ r ac ? + = v omin ?? v ocm ?? i ofs ?? 2 ------------ r ac ? ? = fig 29. 1 v (p-p) differential output with transformer d d d , 2 8 7 $ 3 , 2 8 7 % 3 ' $ & , 2 8 7 $ 3 , 2 8 7 $ 1 , 2 8 7 % 3 , 2 8 7 % 1 9 2 f p 9 9 2 g l i 9 , 2 8 7 $ 1 , 2 8 7 % 1 9 9 9 p $ w r p $ p $ w r p $ dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 42 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.20.2 low input impedance iq-modulator interface the dac1617d1g0 can be easily connected to low input impedance iq-modulators. the image of the local oscillator can be canceled using the digital offset control in the device. figure 31 shows an example of a connection between the dac1617d1g0 and a low input impedance modulator. 10.20.3 iq-modulator - dc interface when the system operation requires to keep the dc component of the spectrum, the dac1617d1g0 can use a dc interface to conn ect an iq-modulator. in this case, the image of the local oscillator can be canceled using the digital offset control in the device. fig 30. 2 v (p-p) differential output with transformer d d d ' $ & , 2 8 7 $ 3 , 2 8 7 $ 1 , 2 8 7 % 3 , 2 8 7 % 1 9 2 f p 9 9 2 g l i 9 9 9 9 p $ w r p $ p $ w r p $ (1) if r int = 100 ? , then r ext = not connected (2) if r int = 200 ? , then r ext =200 ? fig 31. dac1617d1g0 with low input im pedance iq-modulator interface (to be updated) ioutap/ioutbp 3.3 v dac iq modulator 50 r ext r int 50 ioutan/ioutbn auxap/auxbp auxan/auxbn bbap/bbbp bban/bbbn aaa-002450 0 ma to 20 ma low pass filter ioutap/ioutan ioutbp/ioutbn v o(cm) = 2.7 v v o(dif) = 1 v r int = 100 /200 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 43 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating figure 32 shows an example of a connection to an iq modulator with a 1.7 v common input level. figure 33 shows an example of a connection to an iq-modulator with a 3.3 v common input level. fig 32. iq-modulator: dc interface with a 1.7 v common input level fig 33. iq-modulator: dc interface with a 3.3 v common input level , 2 8 7 $ 3 , 2 8 7 % 3 9 ' $ & , 2 8 7 $ 1 , 2 8 7 % 1 % % $ 3 % % % 3 % % $ 3 % % $ 1 % % % 3 % % % 1 9 , f p 9 9 , g l i 9 , 2 8 7 $ 3 , 2 8 7 $ 1 , 2 8 7 % 3 , 2 8 7 % 1 9 2 f p 9 9 2 g l i 9 , 4 p r g x o d w r u 9 , f p 9 % % $ 1 % % % 1 d d d p $ w r p $ o r z s d v v i l o w h u , 2 8 7 $ 3 , 2 8 7 % 3 9 ' $ & , 2 8 7 $ 1 , 2 8 7 % 1 $ 8 ; $ 3 $ 8 ; % 3 $ 8 ; $ 1 $ 8 ; % 1 % % $ 3 % % % 3 % % $ 3 % % $ 1 % % % 3 % % % 1 9 , f p 9 9 , g l i 9 , 2 8 7 $ 3 , 2 8 7 $ 1 , 2 8 7 % 3 , 2 8 7 % 1 9 2 f p 9 9 2 g l i 9 , 4 p r g x o d w r u 9 , f p 9 % % $ 1 % % % 1 d d d p $ w r p $ o r z s d v v i l o w h u dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 44 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating the auxiliary dacs can be used to control the offset withi n an accurate range or with accurate steps. figure 34 shows an example of a connection to an iq-modulator with a 1.7 v common input level and auxiliary dacs. the constraints to adjust the interface are: ? the output compliance range of the dac ? the output complia nce range of the auxiliary dacs ? the input common-mode level of the iq-modulator ? the range of offset correction fig 34. iq-modulator: dc interface with a 1. 7 v common input level and auxiliary dacs 9 ' $ & % % $ 3 % % % 3 % % $ 3 % % $ 1 % % % 3 % % % 1 9 , f p 9 9 , g l i 9 r i i v h w f r u u h f w l r q x s w r p 9 , 2 8 7 $ 3 , 2 8 7 $ 1 , 2 8 7 % 3 , 2 8 7 % 1 9 2 f p 9 9 2 g l i 9 , 4 p r g x o d w r u 9 , f p 9 % % $ 1 % % % 1 d d d p $ w r p $ p $ w \ s l f d o o r z s d v v i l o w h u dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 45 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.20.4 iq-modulator - ac interface use the dac1617d1g0 ac-coupled when the iq-modulator common-mode voltage is close to ground. the auxiliary dacs are required for local oscillator cancelation. figure 35 shows an example of a connection to an iq-modulator with a 0.5 v common input level and auxiliary dacs. 10.21 design recommendations 10.21.1 power and grounding use a separate power supply regulator for the generation of the 1.8 v analog power (pins 65, 62, 55, 69, 72 and 58) and the 1.8 v digital power (pins 12, 19, 36, 26 and 43) to ensure optimal performance. also, include individual lc decoupling fo r the following six sets of power pins: ? v dda(1v8)_p1 (pin 62) ? v dda(1v8)_p2 (pin 65) ? v dda(1v8) (pins 55, 69, 72 and 58) ? v ddd (pins 12, 19, 26, 36, and 43) ? v dda(3v3) (pins 59 and 68) use at least two capacitors for each power pin decoupling. locate these capacitors as close as possible to th e dac1617d1g0 power pins. the die pad is used for both the power dissipation and electrical grounding. insert several vias (7 ? 7 typical) to connect the internal ground plane to the top layer die area. fig 35. iq-modulator: ac interface with a 0. 5 v common input level and auxiliary dacs , 2 8 7 $ 3 , 2 8 7 % 3 , 2 8 7 $ 1 , 2 8 7 % 1 $ 8 ; $ 3 $ 8 ; % 3 $ 8 ; $ 1 $ 8 ; % 1 9 ' $ & q ) q ) 9 n n % % $ 3 % % % 3 % % $ 3 % % $ 1 % % % 3 % % % 1 9 , f p 9 9 , g l i 9 r i i v h w f r u u h f w l r q x s w r p 9 , 2 8 7 $ 3 , 2 8 7 $ 1 , 2 8 7 % 3 , 2 8 7 % 1 9 2 f p 9 9 2 g l i 9 , 4 p r g x o d w r u 9 , f p 9 % % $ 1 % % % 1 d d d p $ w r p $ o r z s d v v i l o w h u dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 46 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22 configuration interface 10.22.1 register description the dac1617d1g0 incorporates more than the 32 spi registers allowed by the address value a[4:0]. it uses three spi register pages (page_00, page_01, and page_0a), each containing 32 registers. the 32nd register of each page indicates which page is currently addressed (00h, 01h or 0ah). page 00h (see table 21) is dedicated to the main control of the dac1617d1g0: ? mode selection ? nco control ? auxiliary dac control ? gain/phase/off set control ? power-down control page 01h (see table 35) is dedicated to: ? multi-device sync hronization (mds) ? dac analog core control (biasing current, sleep mode) page 0ah (see table 53) is dedicated to the lvds input interface configuration. 10.22.2 spi start-up sequence the following spi sequence shows the list of commands to be used to start the dac1627d1g25 in interpolation ? 4 mode, with nco frequency = 153.6 mhz (f dac = 983.04 mhz), pll bypass mode, and without inverse (sin x) / x. other start-up sequences can be easily de rived from this sequence: table 20. spi start-up sequence step spi (address, data) comment 1 write(0x1f, 0x00) select spi (page 0) 2 write(0x00, 0x47) reset spi 3 write(0x01, 0x86) set nco on with positive upper sideband conversion, interpolation ? 4, no inverse (sin x) / x 4 write(0x02, 0xa0) pll in bypass mode 5 write(0x04, 0xff) select nco frequency (freq_nco[7:0]) 6 write(0x05, 0xfc) select nco frequency (freq_nco[15:8]) 7 write(0x06, 0xff) select nco frequency (freq_nco[23:16]) 8 write(0x07, 0xff) select nco frequency (freq_nco[31:24]) 9 write(0x08, 0x27) select nco frequency (freq_nco[39:32]) 10 write(0x1f, 0x01) select spi (page 1) 11 write(0x15,0x0a) set dac_current_6 to 0x0a in order to guaranty good performance over process/temperature/voltage 12 write(0x1f, 0x0a) select spi (page a) dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 47 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 13 write(0x0a, 0x33) specify lvds interf ace setting (no dac a/b swapping, no parity check, no data enable, ?) 14 write(0x0b, 0x01) set cdi block setting (interpolation ? 4, cdi mode) 15 write(0x00, 0x00) release lvds reset (start of the dac1617) table 20. spi start-up sequence ?continued step spi (address, data) comment xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 48 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22.3 page 0 register allocation map table 21 shows an overview of all registers on page 0 (00h in hexadecimal). table 21. page_00 register allocation map address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex 0 00h common r/w 3w_spi spi_rst - - - coding ic_pon gap_pon 1000 0111 87h 1 01h txcfg r/w nco_on nco_lp _sel inv_sin _sel modulation[2:0] interpolation[1:0] 0000 0001 01h 2 02h pllcfg r/w pll_bp pll_buf _pd pll_pll _pd pll_div[1:0] pll_phase[1:0] pll_ osc_pd 1010 0001 a1h 4 04h freqnco_b0 r/w freq_nco[7:0] 0110 0110 66h 5 05h freqnco_b1 r/w freq_nco[15:8] 0110 0110 66h 6 06h freqnco_b2 r/w freq_nco[23:16] 0110 0110 66h 7 07h freqnco_b3 r/w freq_nco[31:24] 0010 0110 66h 8 08h freqnco_b4 r/w freq_nco[39:32] 0010 0110 26h 9 09h ph_corr_ctl0 r/w phase_cor[7:0] 0000 0000 00h 10 0ah ph_corr_ctl1 r/w ph_cor _ena - - phase_cor[12:8] 0000 0000 00h 11 0bh dac_a_dgain_lsb r/w dac_a_dgain[7:0] 1101 0100 50h 12 0ch dac_a_dgain_msb r/w - - - - dac_a_dgain[11:8] 0000 1011 0bh 13 0dh dac_b_dgain_lsb r/w dac_b_dgain[7:0] 1101 0100 50h 14 0eh dac_b_dgain_msb r/w - - - - dac_b_dgain[11:8] 0000 0010 0bh 15 0fh dac_out_ctrl r/w - - - - a_dgain_e b_dgain_e minus _3db clipping _ena 0000 0000 00h xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 49 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 16 10h dac_clipping r/w c lipping_level[7:0] 1111 1111 ffh 17 11h dac_a_offset_lsb r/w dac_a_offset[7:0] 0000 0000 00h 18 12h dac_a_offset_msb r/ w dac_a_offset[15:8] 0000 0000 00h 19 13h dac_b_offset_lsb r/ w dac_b_offset[7:0] 0000 0000 00h 20 14h dac_b_offset_msb r/w dac_b_offset[15:8] 0000 0000 00h 21 15h phinco_lsb r/w ph_nco[7:0] 0000 0000 00h 22 16h phinco_msb r/w ph_nco[15:8] 0000 0000 00h 23 17h dac_a_gain1 r/w dac_a_gain[7:0] 1101 1000 d8h 24 18h dac_a_gain2 r/w dac_a_gain[9:8] - - - - - - 0100 0000 40h 25 19h dac_b_gain1 r/w dac_b_gain[7:0] 1101 1000 d8h 26 1ah dac_b_gain2 r/w dac_b_gain[9:8] - - - - - - 0100 0000 40h 27 1bh dac_a_aux_msb r/w aux_a[9:2] 1000 0000 80h 28 1ch dac_a_aux_lsb r/w aux_a _pon - - - - - aux_a[1:0] 1000 0000 80h 29 1dh dac_b_aux_msb r/w aux_b[9:2] 1000 0000 80h 30 1eh dac_b_aux_lsb r/w aux_b _pon - - - - - aux_b[1:0] 1000 0000 80h 31 1fh page_address r/w - - - - - page[2:0] 0000 0000 00h table 21. page_00 register allocation map ?continued address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 50 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22.4 page 0 bit definition detailed description the tables in this section contain detailed descriptions of the page 0 registers. table 22. register common (address 00h) bit description default values are shown highlighted. bit symbol access value description 7 3w_spi r/w serial interface bus type 0 4-wire spi 13-wire spi 6 spi_rst r/w serial interface reset 0 no reset 1 performs a reset on all registers except address 00h 2 coding r/w coding of input word 0 two?s complement coding 1 unsigned format 1 ic_pon r/w ic power control 0 all circuits (digital and analog, except spi) are in power-down 1 all circuits (digital and analog, except spi) are switched on 0 gap_pon r/w internal band gap power control 0 band gap is power-down 1 internal band gap references are switched on table 23. register txcfg (address 01h) bit description default values are shown highlighted. bit symbol access value description 7 nco_on r/w nco 0 nco disabled, the nco phase is reset to 0 1 nco enabled 6 nco_lp_sel r/w nco low-power selection 0 low-power nco disabled 1 low-power nco enabled (frequency and phase given by the five msb of the registers 06h and 08h, respectively) 5 inv_sin_sel r/w inverse (sin x) / x function selection 0 disable 1 enable 4 to 2 modulation[2:0] r/w modulation 000 dual dac: no modulation 001 positive upper single sideband upconversion 010 positive lower single sideband upconversion 011 negative upper single sideband upconversion 100 negative lower single sideband upconversion others not defined dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 51 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 1 to 0 interpolation[1:0] r/w interpolation 00 no interpolation 01 ? 2 interpolation 10 ? 4 interpolation 11 ? 8 interpolation table 23. register txcfg (address 01h) bit description ?continued default values are shown highlighted. bit symbol access value description table 24. register pllcfg (address 02h) bit description default values are shown highlighted. bit symbol access value description 7 pll_bp r/w pll bypass 0 dac clock generated by pll 1 dac clock provided via external pins clkn and clkp (pll bypass mode) 6 pll_buf_pd r/w pll test buffer control 0 power-down mode 1 enabled 5 pll_pll_pd r/w pll and ckgen control 0 power-down mode 1 enable 4 to 3 pll_div[1:0] r/w pll divider factor 00 f s =2 ? f data 01 f s =4 ? f data 10 f s =8 ? f 11 undefined 2 to 1 pll_phase[1:0] r/w pll phase shift 00 0 degrees phase shift of f s 01 120 degrees phase shift of f s 10 240 degrees phase shift of f s 11 240 degrees phase shift of f s 0 pll_osc_pd r/w pll oscillator output power-down 0 power-down mode 1 enabled table 25. nco frequency registers (add ress 04h to 08h) bit description default values are shown highlighted. address register bit symbol access value description 04h freqnco_b0 7 to 0 freq_nco[7:0] r /w nco frequency (two?s complement coding) - least significant 8 bits for the nco frequency setting 05h freqnco_b1 7 to 0 freq_nco[15:8] r/ w - intermediate 8 bits for the nco frequency setting dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 52 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 06h freqnco_b2 7 to 0 freq_nco[23:16] r/ w - intermediate 8 bits for the nco frequency setting 07h freqnco_b3 7 to 0 freq_nco[31:24] r/ w - intermediate 8 bits for the nco frequency setting 08h freqnco_b4 7 to 0 freq_nco[39:32] r/w - most significant 8 bits for the nco frequency setting table 25. nco frequency registers (add ress 04h to 08h) bit description ?continued default values are shown highlighted. address register bit symbol access value description table 26. dac output phase correction registers (address 09h to 0ah) bit description default values are shown highlighted. address register bit symbol access value description 09h ph_corr_ctl0 7 to 0 phase_cor[7:0] r/w dac output phase correction factor (lsb) - least significant 8 bits for the dac output phase correction factor 0ah ph_corr_ctl1 7 ph_cor_ena r/w dac output phase correction control 0 dac output phase correction disabled 1 dac output phase correction enabled 4 to 0 phase_cor[12:8] r/w dac output phase correction factor msb 00000 most significant 5 bits for the dac output phase correction factor table 27. digital gain control registers (address 0bh to 0eh) bit description default values are shown highlighted. address register bit symbol access value description 0bh dac_a_dgain_lsb 7 to 0 dac_a_dgain[7:0] r/w dac a digital gain control - least significant 8 bits for the dac a digital gain 0ch dac_a_dgain_msb 3 to 0 dac_a_dgain[11:8] - most significant 4 bits for the dac a digital gain 0dh dac_b_dgain_lsb 7 to 0 dac_b_dgain[7:0] r/w dac b digital gain control - least significant 8 bits for the dac b digital gain 0eh dac_b_dgain_msb 3 to 0 dac_b_dgain[11:8] - most significant 4 bits for the dac b digital gain table 28. register dac_out_ctrl (address 0fh) default values are shown highlighted. bit symbol access value description 3 a_dgain_e r/w dac a digital gain control 0 disable 1 enable dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 53 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 2 b_dgain_e r/w dac b digital gain control 0 disable 1 enable 1 minus_3db r/w dac attenuation control 0 unity gain 1 ? 3 db gain 0 clipping_ena r/w digital dac output clipping control 0 disable 1 enable table 28. register dac_out_ctrl (address 0fh) ?continued default values are shown highlighted. bit symbol access value description table 29. register dac_clipping (address 10h) default values are shown highlighted. bit symbol access value description 7 to 0 clipping_level[7:0] r/w - digital dac output clipping level value table 30. digital offset value registers (address 11h to 14h) bit description default values are shown highlighted. address register bit symbol access value description 11h dac_a_offset_lsb 7 to 0 dac_a_offset[7:0] r/w dac a digital offset value - least significant 8 bits for the dac a digital offset 12h dac_a_offset_msb 7 to 0 dac_a_offset[15:8] - most significant 8 bits for the dac a digital offset 13h dac_b_offset_lsb 7 to 0 dac_b_offset[7:0] r/w dac b digital offset value - least significant 8 bits for the dac b digital offset 14h dac_b_offset_msb 7 to 0 dac_b_offset[15:8] - most significant 8 bits for the dac b digital offset table 31. nco phase offset registers (address 15h to 16h) bit description default values are shown highlighted. address register bit symbol access value description 15h phinco_lsb 7 to 0 ph_nco[7:0 ] r/w nco phase offset lsb - least significant 8 bits for the nco phase setting 16h phinco_msb 7 to 0 ph_nco[15: 8] r/w nco phase offset msb - most significant 8 bits for the nco phase setting dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 54 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 32. analog gain control registers (address 17h to 1ah) bit description default values are shown highlighted. address register bit symbol access value description 17h dac_a_gain1 7 to 0 dac _a_gain[7:0] r/w - dac a analog gain control (lsb) 18h dac_a_gain2 7 to 6 dac _a_gain[9:8] r/w - dac a analog gain control (msb) 19h dac_b_gain1 7 to 0 dac _b_gain[7:0] r/w - dac b analog gain control (lsb) 1ah dac_b_gain2 7 to 6 dac _b_gain[9:8] r/w - dac b analog gain control (msb) table 33. auxiliary dac registers (add ress 1bh to 1eh) bit description default values are shown highlighted. address register bit symbol access value description 1bh dac_a_aux_msb 7 to 0 aux_a[9:2] r/w - most significant 8 bits for auxiliary dac a 1ch dac_aux_lsb 7 aux_a_pon r/w auxiliary dac a power 0off 1on 1 to 0 aux_a[1:0] r/w - least signi ficant 2 bits for auxiliary dac a 1dh dac_b_aux_msb 7 to 0 aux_b[9:2] r/w - most significant 8 bits for auxiliary dac b 1eh dac_b_aux_lsb 7 aux_b_pon r/w auxiliary dac b power 0off 1on 1 to 0 aux_b[1:0] r/w - least signi ficant 2 bits for auxiliary dac b table 34. spi_page register (a ddress 1fh) bit description default values are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w - spi page address xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 55 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22.5 page 1 allocation map table 35 shows an overview of all registers on page 1 (01h in hexadecimal). table 35. page 1 register allocation map address register name r/w bit definition default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex 0 00h mds_main r/w mds_eqcheck[1:0] mds_ run mds_ nco mds_ nco_ pulse mds_ sref_ dis mds_ master mds_ ena 0000 0100 04h 101hmds_win_ period_a r/w mds_win_period_a[7:0] 1000 0000 80h 202hmds_win_ period_b r/w mds_win_period_b[7:0] 0100 0000 40h 303hmds_ misccntrl0 r/w - - - mds_ eval_ ena mds_ prerun_e mds_pulsewidth[2:0] 0001 0000 10h 404hmds_man_ adjustdly r/w mds_ man mds_man_adjustdly[6:0] 0100 0000 40h 5 05h mds_auto_ cycles r/w mds_auto_cycles[7:0] 1000 0000 80h 606hmds_ misccntrl1 r/w mds_sr_ cken mds_sr_ lockout mds_ sr_lock mds_ relock mds_lock_delay[3:0] 0000 1111 0fh 707hmds_ offset_dly rw - - - mds_offset_dly[4:0] 0000 0000 00h 808hmds_ adjdelay rw - mds_adjdelay[6:0] 0000 0000 00h 909hmds_ status0 r early late equal mds_eq early_ error late_ error equal_ found mds_ active uuuu uuuu uuh 10 0ah mds_ status1 r - - add_err mds_en_phase[1:0] mds_ prerun mds_ lockout mds_ lock uuuu uuuu uuh 11 0bh intr_ctrl r/w - - - - - intr_ clear intr_mon_dclk_ range 0000 0100 04h 12 0ch intr_en r/w maqb_en maqa_en auto_dl_ en auto_cal _en flag_dl_e n lclksamp_ en parber_ en mon_dclk _en 0000 0000 00h 13 0dh intr_flags r maqb_ rdy maqa_ rdy auto_ dl_rdy auto_ cal_rdy flag_ dl_err lclksamp_ err parber_ err mon_dclk _err uuuu uuuu uuh xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 56 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating [1] u = undefined at power-up or after reset. 14 0eh dac_ current_ aux r/w - - - - dac_aux_bias[3:0] 0000 0111 07h 15 0fh dac_ current_0 r/w - - - - dac_dig_bias[3:0] 0000 0111 07h 16 10h dac_ current_1 r/w - - - - dac_mst_bias[3:0] 0000 0111 07h 17 11h dac_ current_2 r/w - - - - dac_drv_bias[3:0] 0000 0111 07h 18 12h dac_ current_3 r/w - - - - dac_slv_bias[3:0] 0000 0111 07h 19 13h dac_ current_4 r/w - - - - dac_ck_bias[3:0] 0000 0111 07h 20 14h dac_ current_5 r/w - - - - dac_cas_bias[3:0] 0000 0111 07h 21 15h dac_ current_6 r/w - - - - dac_com_bias[3:0] 0000 0111 07h 22 16h dac_pon_ sleep r/w dac_b_ pon dac_b_ sleep dac_b_ com_pd dac_b_ bleed_ pd dac_a_ pd dac_a_ sleep dac_a_ com_pd dac_a_ bleed_ pd 10111 011 bbh 23 17h dac_clkdig_ delay r/w - - - - - pll_dig_delay[2:0] 0000 0010 02h 31 1fh page_ address r/w - - - - - page[2:0] 0000 0000 00h table 35. page 1 register allocation map ?continued address register name r/w bit definition default [1] bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 57 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22.6 page 1 bit definition detailed description the tables in this section contain detailed descriptions of the page 1 registers. table 36. mds_main register (address 00h) bit description default values are shown highlighted. bit symbol access value description 7 to 6 mds_eqcheck[1:0] r/w lock mode 00 lock when (early = 1 and late = 1) 01 lock when (early = 1, late = 1 and equal = 1) 10 lock when equal = 1 11 force lock (equal-check = 1) 5 mds_run r/w evaluation process restart control 0 no action 1(0 ? 1) transition restarts evaluation_counter 4 mds_nco r/w nco synchronization 0 no action 1 enable 3 mds_nco_pulse r/w nco pulse 0 no action 1 manual control nco tuning 2 mds_sref_dis r/w internal pulse generation 0 normal mode 1 disable 1 mds_master r/w mds mode selection 0 slave mode 1 master mode 0 mds_ena r/w mds function control 0 disable 1 enable table 37. mds window time registers (address 01h to 02h) bit description legend: * reset value; <= mandatory value address register bit symbol access value description 01h mds_win_period_a 7 to 0 mds_win_ period_a[7:0] r/w - determines mds window low time 02h mds_win_period_b 7 to 0 mds_win_ period_b[7:0] r/w - determines mds window high time table 38. mds_misccntrl0 register (address 03h) bit description default values are shown highlighted. bit symbol access value description 4 mds_eval_ena r/w mds evaluation 0 disable 1 enable dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 58 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 3 mds_prerun_ena r/w automatic mds start-up 0 no mds_win/mds_ref generation in advance 1 mds_win/mds_ref run-in before mds_evaluation 2 to 0 mds_pulsewidth[2:0] r/w width of mds (in output clock -periods) 000 1 dac clock period 001 2 dac clock periods 010 to 111 (mds_pulsewidth ? 1) ? 4 dac clock periods table 38. mds_misccntrl0 register (address 03h) bit description ?continued default values are shown highlighted. bit symbol access value description table 39. mds_man_adjustdly register (address 04h) bit description default values are shown highlighted. bit symbol access value description 7 mds_man r/w adjustment delays mode 0 auto-control adjustment delays 1 manual control adjustment delays 6 to 0 mds_man_adjustdly[6:0 ] r/w adjustment delay value - if mds_man = 0 then initial value adjustment delay - if mds_man = 1 then controls adjustment delay table 40. mds_auto_cycles register (address 05h) bit description default values are shown highlighted. bit symbol access value description 7 to 0 mds_auto_cycles[7:0] r/w - number of ev aluation cycles applied fo r mds. if set to 255, the ic continuously generates/monitors the mds pulse table 41. mds_misccntrl1 register (address 06h) bit description default values are shown highlighted. bit symbol access value description 7 mds_sr_cken r/w - lock mode 0 free-running mds_sr_cken 1 mds_sr_cken forced low 6 mds_sr_lockout r/w lockout detector soft reset 0 mds_sr_lockout in use 1 mds_sr_lockout forced low 5 mds_sr_lock r/w lock detector soft reset 0 mds_sr_lock in use 1 mds_sr_lock forced low 4 mds_relock r/w relock mode 0 no action 1 relock when lockout occurs 3 to 0 mds_lock_delay[3:0] r/w - number of succeeding 'equal' detections until lock dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 59 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 42. mds_offset_dly register (address 07h) bit description default values are shown highlighted. bit symbol access value description 4 to 0 mds_offset_dly[6:0] r/w - delay of fset for dataflow (two?s complement [ ? 16 to 15] table 43. mds_adjdelay register (address 08h) bit description default values are shown highlighted. bit symbol access value description 6 to 0 mds_adjdelay[6:0] r - ac tual value adjustment delay table 44. mds status registers (add ress 09h to 0ah) bit description default values are shown highlighted. address register bit symbol access value description 09h mds_status0 7 early r early signal (sampled) from early-to-late detector 0false 1true 6 late r late signal (sampled) from early-to-late detector 0false 1true 5 equal r equal signal (sampled) from early-to-late detector 0false 1true 4 mds_lock r result equal-check 0false 1true 3 early_error r adjustment delay maximum value stops the search 0false 1true 2 late_error r adjustment delay minimum value stops the search 0false 1true 1 equal_found r evaluation logic has detected equal condition 0false 1true 0 mds_active r evaluation logic active 0false 1true dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 60 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 0ah mds_status1 5 add_err r adjustment delay error detection 0ok 1 delay offset cannot be applied in available range 4 to 3 mds_en_phase[1:0] r mds enable phase 00 enable phase = 0 01 enable phase = 1 (only for ? 2) 10 enable phase = 2 (only for ? 2and ? 4) 11 enable phase = 3 (only for ? 2) 2 mds_prerun r mds-prerun phase active flag 0false 1true 1 mds_lockout r mds_lockout detected flag 0false 1true 0 mds_lock r mds_lock flag 0false 1true table 44. mds status registers (add ress 09h to 0ah) bit description ?continued default values are shown highlighted. address register bit symbol access value description table 45. interrupt control register (address 0bh) bit description default values are shown highlighted. bit symbol access value description 3 intr_ctrl r/w internal interrupt and flags clearance 0 disabled 1enabled 2 to 0 intr_mon_dclk_range r/w interrupt cond ition as related to the dclk monitoring 00 mon_dclk_flag when mon_dclk drifts to (1 or 5) (detect small drift) 01 mon_dclk_flag when mon_dclk drifts to (2 or 4) (detect large drift) 10 mon_dclk_flag when mon_dclk drifts to (3) (detect maximum drift) 11 mon_dclk_flag disabled dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 61 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 46. interrupt enable register (address 0ch) bit description default values are shown highlighted. bit symbol access value description 7 maqb_en r/w acquisition module b interrupt 0 disabled 1 enabled 6 maqa_en r/w acquisition module a interrupt 0 disabled 1 enabled 5 auto_dl_en r/w automatic download mtp interrupt 0 disabled 1 enabled 4 auto_cal_en r/w lvds automatic calibration interrupt 0 disabled 1 enabled 3 flag_dl_en r/w mtp download error interrupt 0 disabled 1 enabled 2 lclksamp_en r/w lclk sampling monitor error interrupt 0 disabled 1 enabled 1 parber_en r/w lvds parity or ber error interrupt 0 disabled 1 enabled 0 mon_dclk_en r/w dclk monitor error interrupt 0 disabled 1 enabled table 47. intr_flags register (address 0dh) bit description default values are shown highlighted. bit symbol access value description 7 maqb_rdy r acquisition module b status 0not ready 1 ready 6 maqa_rdy r acquisition module a status 0not ready 1 ready 5 auto_dl_rdy r automatic download mtp status 0not ready 1 ready 4 auto_cal_rdy r lvds automatic calibration status 0not ready 1 ready dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 62 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating [1] all default values (except for register dac_current_6) are ok for good performance over process voltage and temperature. [2] the register dac_current_6 (address 0x15) must be set to 0x0a. 3 flag_dl_err r error during mtp download 0 no error 1 error detected 2 lclksamp_err r error on lclk sampling monitor 0 no error 1 error detected 1 parber_err r error on lvds parity or ber error 0 no error 1 error detected 0 mon_dclk_err r error on dclk monitor 0 no error 1 error detected table 47. intr_flags register (address 0dh) bit description ?continued default values are shown highlighted. bit symbol access value description table 48. bias current control registers (address 0eh to 15h) bit description default values are shown highlighted. address register bit symbol access value description 0eh dac_current_aux 3 to 0 dac_aux_bias[3:0] r/w - bias current control (see table 49) 0fh dac_current_0 3 to 0 dac_dig_bias[3:0] r/w - 10h dac_current_1 3 to 0 dac_mst_bias[3:0] r/w - 11h dac_current_2 3 to 0 dac_drv_bias[3:0] r/w - 12h dac_current_3 3 to 0 dac_slv_bias[3:0] r/w - 13h dac_current_4 3 to 0 dac_ck_bias[3:0] r/w - 14h dac_current_5 3 to 0 dac_cas_bias[3:0] r/w - 15h dac_current_6 3 to 0 dac_com_bias[3:0] r/w - table 49. bias current control table bias[3:0] deviation from nominal current 0 0 0 0 ? 35 % 0 0 0 1 ? 30 % 0 0 1 0 ? 25 % 0 0 1 1 ? 20 % 0 1 0 0 ? 15 % 0 1 0 1 ? 10 % 0 1 1 0 ? 5% 0 1 1 1 +0 % (default) 1 0 0 0 +5 % 1 0 0 1 +10 % 1 0 1 0 +15 % dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 63 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 1 0 1 1 +20 % 1 1 0 0 +25 % 1 1 0 1 +30 % 1 1 1 0 +35 % 1 1 1 1 +40 % table 49. bias current control table ?continued bias[3:0] deviation from nominal current table 50. dac_pon_sleep register (address 16h) bit description default values are shown highlighted. bit symbol access value description 7 dac_b_pon r/w - dac b power control 0 power-down 1 power on 6 dac_b_sleep r dac b mode selection 0 normal operation 1 sleep mode 5 dac_b_com_pd r commutator b control 0 disable (power-down) 1 enable 4 dac_b_bleed_pd r dac b bleed current control 0 disable (power-down) 1 enable 3 dac_a_pon r dac a power control 0 power-down 1 power on 2 dac_a_sleep r dac b mode selection 0 normal operation 1 sleep mode 1 dac_a_com_pd r commutator a control 0 disable (power-down) 1 enable 0 dac_a_bleed_pd r dac a bleed current control 0 disable (power-down) 1 enable table 51. dac_test_8 register (a ddress 17h) bit description default values are shown highlighted. bit symbol access value description 2 to 0 pll_dig_delay[2:0] r/w - digital cl ock delay offset of pll/ckgen_div8 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 64 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 52. spi_page register (a ddress 1fh) bit description default values are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w - spi page address xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 65 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22.7 page a register allocation map table 53 shows an overview of all registers on page a (0ah in hexadecimal). table 53. page_0a register allocation map address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex 0 00h main_cntrl r/w - - - ld_pd pd_cntrl cal_ cntrl rst_ dckl rst_ lckl 0000 0011 03h 1 01h man_ldclkdel r/w - - - - ldclk_del[3:0] 0000 0000 00h 2 02h dbg_lvds r/w - - - - sber reserved 0000 0000 00h 4 04h rst_ext_ldclk r/w rst_ext_lclk_time[7:0] 0011 1111 3fh 5 05h rst_ext_dclk r/w rst_ext_dclk_time[7:0] 0010 0000 20h 6 06h dcmsu_prediv r/w dcmsu_predivider[7:0] 0001 1101 1dh 8 08h ld_pol_lsb r/w ld_pol[7:0] 0000 0000 00h 9 09h ld_pol_msb r/w ld_pol[15:8] 0000 0000 00h 10 0ah ld_cntrl r/w parityc descra mble sel_en[1:0] word_swap ldab_ swap iq_ format edge_ ldclk 0000 0011 03h 11 0bh misc_cntrl r/w sr_cdi reserved i_lev_ cntrl[1:0] q_lev_cntrl[1:0] cdi_mode[1:0] 0000 0000 00h 12 0ch i_dc_lvl_lsb r/w i_dc_level[7:0] 0000 0000 00h 13 0dh i_dc_lvl_msb r/w i _dc_level[15:8] 1000 0000 80h 14 0eh q_dc_lvl_lsb r/w q _dc_level[7:0] 0000 0000 00h 15 0fh q_dc_lvl_msb r/w q_dc_level[15:8] 1000 0000 80h 16 10h io_mux0 r/w io_ select0[7:0] 1111 1111 ffh xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 66 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 17 11h io_mux1 r/w io_select1[7:0] 1111 1111 ffh 18 12h io_mux2 r/w io_select1[9 :8] - io_select0[9:8] - 1111 1111 ffh 27 1bh type_id r dac frontend[1:0] dual dsp[1:0] bit_res[1:0] 0011 1010 3ch 28 1ch dac_version r dac _version_id[7:0] 0010 1001 29h 29 1dh dig_version r dig_version_id[7:0] 0000 0100 04h 30 1eh ld_version r lvds_ version_id[7:0] 0000 1001 09h 31 1fh page_address r/w - - - - - page[2:0] 0000 0000 00h table 53. page_0a register allocation map ?continued address register name r/w bit definition default bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bin hex dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 67 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 10.22.8 page a bit definition detailed description the tables in this section contain detailed descriptions of the page a registers. table 54. register main_cntrl (address 00h) default values are shown highlighted. bit symbol access value description 4 ld_pd r/w lvds interface power-down (control possible only when pd_cntrl = 1) 0 switched on 1 switched off 3 pd_cntrl r/w power-down modes controlled by 0 dcmsu block 1 spi registers 2 cal_cntrl r/w compensation delay controlled by 0 dcmsu block (automatic calibration) 1 spi registers (manual control) 1 rst_dclk r/w reset dclk 0 disable 1 enable 0 rst_lclk r/w reset lvds clock 0 disable 1 enable table 55. register man_ldclkdel (address 01h) default values are shown highlighted. bit symbol access value description 3 to 0 ldclk_del[3:0] r/w lvds clock compensation delay (control only if cal_cntrl = 1) - 4-bit compensation delay for lvds clock table 56. register dbg_lvds (address 02h) default values are shown highlighted. bit symbol access value description 3 sber r/w simple ber control 0 no action 1 simple ber active 2 to 0 reserved r/w 000 reserved dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 68 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 57. extension time reset registers (address 04h to 05h) bit description default values are shown highlighted. address register bit symbol access value description 04h rst_ext_lclk 7 to 0 rst_ext_lclk_ time[7:0] r/w specifies extension time reset, expressed in lvds clock periods - 8 bits for the extension time reset 05h rst_ext_dclk 7 to 0 rst_ext_dclk_ time[7:0] r/w specify extension time reset, expressed in dclk periods - 8 bits for the extension time reset table 58. register dcsmu_prediv (address 06h) default values are shown highlighted. bit symbol access value description 7 to 0 dcmsu_predivider[7:0] r/w predivider value for the dcmsu, expressed in lvds clock period - 8 bits for the predivider value table 59. lsb/msb of polarity registers (address 08h to 09h) bit description default values are shown highlighted. address register bit symbol access value description 08h ld_pol_lsb 7 to 0 ld_pol[7:0] r/w toggles polarity of corresponding bit pair within ld[7:0] - most significant 6 bits for the polarity toggle 09h ld_pol_msb 7 to 0 ld_pol[15:8] - most significant 6 bits for the polarity toggle table 60. register ld_cntrl (address 0ah) default values are shown highlighted. bit symbol access value description 7 parityc r/w parity check 0 disable 1 enable 6 descramble r/w descramble control 0 disable descrambling 1 enable descrambling 5 to 4 sel_en[1:0] r/w ldvs data enable 00 lvds data enable = align signal from channel a 01 lvds data enable = align signal from channel b 10 lvds data enable = 0 11 lvds data enable = 1 3 word_swap r/w reverse order for lvds path 0 normal operation 1 msb to lsb order reversed dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 69 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 2 ldab_swap r/w swaps lvds a and lvds b paths 0 normal operation 1 lvds a and lvds b paths are swapped 1 iq_format r/w specify iq supplied format 0 folded 1 interleaved 0 edge_ldclk r/w specify sampling edge for lvds data path 0 falling edge of ldclk 1 rising edge of ldclk table 60. register ld_cntrl (address 0ah) ?continued default values are shown highlighted. bit symbol access value description table 61. register misc_cntrl (address 0bh) default values are shown highlighted. bit symbol access value description 7 sr_cdi r/w cdi block software reset control 0 no action 1 perform a software reset on cdi 6 reserved r/w 0 reserved 5 to 4 i_lev_cntrl[1:0] r/w specifies output from cdi for i path 00 normal operation (cdi data output sent to digital signal processing input) 01 if ldvs data enable = 1, then normal operation; if ldvs data enable = 0, then digital signal processing input = i_dc_level register value 10 digital signal proc essing input = i_dc_level 11 digital signal proc essing input = i_dc_level 3 to 2 q_lev_cntrl[1:0] r/w specif ies output from cdi for q path 00 normal operation (cdi data output sent to digital signal processing input) 01 if ldvs data enable = 1, then normal operation; if ldvs data enable = 0, then digital signal processing input = q_dc_level register value 10 digital signal proc essing input = q_dc_level 11 digital signal proc essing input = q_dc_level 1 to 0 cdi_mode[1:0] r/w specifies cdi mode 00 cdi_mode 0 ( ? 2 mode) 01 cdi_mode 1 ( ? 4 mode) 10 cdi_mode 2 ( ? 8 mode) 11 not used dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 70 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 62. lds/mds of i/q dc levels registers (address 0ch to 0fh) bit description default values are shown highlighted. address register bit symbol access value description 0ch i_dc_lvl_lsb 7 to 0 i_dc_level[7:0] r/w i_dc_level - least significant 8 bits for i_dc_level 0dh i_dc_lvl_msb 7 to 0 i_dc_level[15:8] - most significant 8 bits for i_dc_level 0eh q_dc_lvl_lsb 7 to 0 q_dc_level[7:0] r/w q_dc_level - least significant 8 bits for q_dc_level 0fh q_dc_lvl_msb 7 to 0 q_dc_level[1 5:8] - most significant 8 bits for q_dc_level table 63. register io_mux0 and io_mux2 (address 10h and 12h) default values are shown highlighted. io_select0[9:0] signal on pin io0 description 00 0000 0000 lclk internal lvds lclk clock 00 0000 0001 ringo internal low frequency oscillator (approximately 1 mhz) 01 0000 nnnn ldout_a dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 71 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 64. register io_mux1 and io_mux2 (address 11h and 12h) default values are shown highlighted. io_select1[9:0] signal on pin io1 description 00 0000 0000 dclk internal dclk clock (f s /8 frequency) 01 0000 nnnn ldout_b dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 72 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating table 66. register dac_version (address 1ch) default values are shown highlighted. bit symbol access value description 7 to 0 dac_version_id[7:0] r dac version number - 8 bits for the dac version number table 67. register dig_version (address 1dh) default values are shown highlighted. bit symbol access value description 7 to 0 dig_version_id[7:0] r digital version number - 8 bits for the digital version number table 68. register lvds_version (address 1eh) default values are shown highlighted. bit symbol access value description 7 to 0 lvds_version_id[7:0] r l vds receiver version number - 8 bits for the lvds receiver version number table 69. register page_add (address 1fh) default values are shown highlighted. bit symbol access value description 2 to 0 page[2:0] r/w page address - current page address dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 73 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 11. package outline fig 36. package outline sot813-3 (hvqfn72) references outline version european projection issue date iec jedec jeita sot813-3 - - - - - - - - - sot813-3_po 10-04-02 11-06-20 unit mm max nom min 1.00 0.85 0.80 0.05 0.02 0.00 0.2 10.1 10.0 9.9 7.2 7.1 7.0 10.1 10.0 9.9 0.5 8.5 0.5 0.4 0.3 0.1 a dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn72: plastic thermal enhanced very thin quad flat package; no leads; 72 terminals; body 10 x 10 x 0.85 mm sot813-3 a 1 b 0.30 0.21 0.18 cd (1) d h e (1) e h 7.2 7.1 7.0 ee 1 e 2 8.5 lv 0.1 w 0.05 y 0.05 y 1 0 5 10 mm scale terminal 1 index area b a d e c y c y 1 x detail x a c a 1 b e 2 e 1 e e 1/2 e 1/2 e a c b v c w terminal 1 index area d h e h 1 18 l 19 36 37 54 55 72 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 74 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 12. abbreviations table 70. abbreviations acronym description bw bandwidth bwa broadband wireless access cdi clock domain interface cdma code division multiple access cml current mode logic cmos complementary metal oxide semiconductor dac digital-to-analog converter edge enhanced data rates for gsm evolution fir finite impulse response gsm global system for mobile communications if intermediate frequency imd3 third order intermodulation lmds local multipoint distribution service lo local oscillator lvds low-voltage differential signaling nco numerically controlled oscillator nmos negative metal-oxide semiconductor pll phase-locked loop sfdr spurious-free dynamic range spi serial peripheral interface wcdma wide band code division multiple access wll wireless local loop dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 75 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 13. glossary 13.1 static parameters inl ? the deviation of the transfer function from a best fit straight line (linear regression computation). dnl ? the difference between the ideal and the measured output value between successive dac codes. 13.2 dynamic parameters spurious-free dynamic range (sfdr) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. decibels relative to full scale (dbfs) ? unit used in a digital system to measure the amplitude level in decibel rela tive to the maximum peak value. intermodulation distortion (imd) ? from a dual-tone digital input sine wave (these two frequencies being close together), the intermodulation distortion products imd2 and imd3 (second order and third order components) are defined below. imd2 ? the ratio between the rms value of either tone and the rms value of the worst second order intermodulation product. imd3 ? the ratio between the rms value of either tone and the rms value of the worst third order intermodulation product. total harmonic distortion (thd) ? the ratio between the rms value of the harmonics of the output frequency and the rms valu e of the output sine wave. usually, the calculation of thd is done on the first 5 harmonics. signal-to-noise ratio (snr) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the noise excluding the harmonics and the dc component. restricted bandwidth spurious-free dynamic range (sfdr rbw ) ? the ratio between the rms value of the reconstructed output sine wave and the rms value of the noise, including the harmonics, in a given bandwidth centered around f offset . dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 76 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 14. revision history 15. contact information for more information or sales office addresses, please visit: http://www.idt.com table 71. revision history document id release date data sheet status change notice supersedes dac1617d1g0 v.3 20120702 rebranded/updated - dac1617d1g0 v.2 dac1617d1g0 v.2 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 77 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 16. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4 table 3. limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 4. thermal characteristics . . . . . . . . . . . . . . . . . . .7 table 5. characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 6. read or write mode access description . . . . .15 table 7. number of bytes transferred . . . . . . . . . . . . . .15 table 8. spi timing characteristic s . . . . . . . . . . . . . . . .16 table 9. input lvds bus swapping . . . . . . . . . . . . . . . .18 table 10. folded and interleaved format mapping . . . . . .19 table 11. cdi mode 0: operating modes examples . . . .25 table 12. cdi mode 1: operating modes examples . . . .25 table 13. cdi mode 2: operating modes examples . . . .26 table 14: interpolation filter coeffi cients . . . . . . . . . . . . .27 table 15. complex modulator operation mode . . . . . . . .30 table 16. inversion filter coefficients . . . . . . . . . . . . . . . .31 table 17. dac transfer function . . . . . . . . . . . . . . . . . . .36 table 18. digital offset adjustment . . . . . . . . . . . . . . . . .38 table 19. auxiliary dac transfer function . . . . . . . . . . . .40 table 20. spi start-up sequence . . . . . . . . . . . . . . . . . . .46 table 21. page_00 register allocation map . . . . . . . . . . .48 table 22. register common (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 table 23. register txcfg (address 01h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .50 table 24. register pllcfg (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .51 table 25. nco frequency registers (address 04h to 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .51 table 26. dac output phase correction registers (address 09h to 0ah) bit description . . . . . . . .52 table 27. digital gain control registers (address 0bh to 0eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .52 table 28. register dac_out_ctrl (address 0fh) . . .52 table 29. register dac_clipping (address 10h) . . . . .53 table 30. digital offset value registers (address 11h to 14h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 31. nco phase offset r egisters (address 15h to 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .53 table 32. analog gain control registers (address 17h to 1ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 33. auxiliary dac registers (address 1bh to 1eh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 34. spi_page register (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .54 table 35. page 1 register alloca tion map . . . . . . . . . . . .55 table 36. mds_main register (address 00h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 table 37. mds window time registers (address 01h to 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 table 38. mds_misccntrl0 register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .57 table 39. mds_man_adjustdl y register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 40. mds_auto_cycles register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 41. mds_misccntrl1 register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 42. mds_offset_dly register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 43. mds_adjdelay register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 44. mds status registers (address 09h to 0ah) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 45. interrupt control register (address 0bh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 46. interrupt enable register (address 0ch) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 47. intr_flags register (address 0dh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 48. bias current control registers (address 0eh to 15h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 49. bias current control table . . . . . . . . . . . . . . . . 62 table 50. dac_pon_sleep register (address 16h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 51. dac_test_8 register (address 17h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 52. spi_page register (address 1fh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 53. page_0a register allocation map . . . . . . . . . . 65 table 54. register main_cntrl (address 00h) . . . . . . 67 table 55. register man_ldclkdel (address 01h) . . . 67 table 56. register dbg_lvds (address 02h) . . . . . . . . 67 table 57. extension time reset registers (address 04h to 05h) bit description . . . . . . . . 68 table 58. register dcsmu_prediv (address 06h) . . . 68 table 59. lsb/msb of polarity registers (address 08h to 09h) bit description . . . . . . . . 68 table 60. register ld_cntrl (address 0ah) . . . . . . . . 68 table 61. register misc_cntrl (address 0bh) . . . . . . 69 table 62. lds/mds of i/q dc levels registers (address 0ch to 0fh) bit description . . . . . . . . 70 table 63. register io_mux0 and io_mux2 (address 10h and 12h) . . . . . . . . . . . . . . . . . . 70 table 64. register io_mux1 and io_mux2 (address 11h and 12h) . . . . . . . . . . . . . . . . . . 71 table 65. register type_id (address 1bh) . . . . . . . . . . 71 table 66. register dac_version (address 1ch) . . . . 72 table 67. register dig_version (address 1dh) . . . . . 72 table 68. register lvds_version (address 1eh) . . . . 72 table 69. register page_add (address 1fh) . . . . . . . . 72 table 70. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 71. revision history . . . . . . . . . . . . . . . . . . . . . . . . 76 dac1617d1g0 3 ? idt 2012. all rights reserved. preliminary data sheet rev. 03 ? 2 july 2012 78 of 78 integrated device technology dac1617d1g0 dual 16-bit dac: up to 1 gsps; x2, x4 and x8 interpolating 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 thermal characteristics . . . . . . . . . . . . . . . . . . 7 9 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 10 application information. . . . . . . . . . . . . . . . . . 14 10.1 general description . . . . . . . . . . . . . . . . . . . . 14 10.2 serial peripheral interfac e (spi) . . . . . . . . . . . 14 10.2.1 protocol description . . . . . . . . . . . . . . . . . . . . 14 10.2.2 spi timing description . . . . . . . . . . . . . . . . . . . 16 10.3 power-on sequence . . . . . . . . . . . . . . . . . . . . 16 10.4 lvds data input format (dif) block . . . . . . . 17 10.4.1 input port polarity . . . . . . . . . . . . . . . . . . . . . . 17 10.4.2 input port mapping . . . . . . . . . . . . . . . . . . . . . 17 10.4.3 input port swapping . . . . . . . . . . . . . . . . . . . . 18 10.4.4 input port formatting . . . . . . . . . . . . . . . . . . . . 19 10.4.5 data parity/data enable. . . . . . . . . . . . . . . . . . 20 10.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 10.6 general-purpose io pins . . . . . . . . . . . . . . . . 20 10.7 input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10.7.1 lvds ddr clock. . . . . . . . . . . . . . . . . . . . . . . 20 10.7.2 dac core clock . . . . . . . . . . . . . . . . . . . . . . . . 21 10.8 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10.9 operating modes . . . . . . . . . . . . . . . . . . . . . . 24 10.9.1 cdi mode 0 (x2 interpolation). . . . . . . . . . . . . 25 10.9.2 cdi mode 1 (x4 interpolation). . . . . . . . . . . . . 25 10.9.3 cdi mode 2 (x8 interpolation). . . . . . . . . . . . . 26 10.10 fir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.11 single sideband modulator (ssbm). . . . . . . . 29 10.11.1 nco in 40 bits . . . . . . . . . . . . . . . . . . . . . . . . 29 10.11.2 nco low power . . . . . . . . . . . . . . . . . . . . . . . 30 10.11.3 complex modulator . . . . . . . . . . . . . . . . . . . . 30 10.11.4 minus 3db. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.12 inverse (sin x) / x . . . . . . . . . . . . . . . . . . . . . . 31 10.13 multiple devices synchronization (mds). . . . 31 10.13.1 mds concept . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.13.1.1 mds in all slaves mode . . . . . . . . . . . . . . . . . 34 10.13.1.2 mds in master/slaves mode . . . . . . . . . . . . . 35 10.13.2 mds flexibility and constraints . . . . . . . . . . . . 35 10.14 dac transfer function. . . . . . . . . . . . . . . . . . . 36 10.15 full-scale current . . . . . . . . . . . . . . . . . . . . . . 37 10.15.1 regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.15.2 full-scale current adjustment. . . . . . . . . . . . . 37 10.16 limiter/clip control . . . . . . . . . . . . . . . . . . . . . 38 10.17 digital offset adjustment. . . . . . . . . . . . . . . . . 38 10.18 analog output. . . . . . . . . . . . . . . . . . . . . . . . . 38 10.19 auxiliary dacs . . . . . . . . . . . . . . . . . . . . . . . . 39 10.20 output configuration. . . . . . . . . . . . . . . . . . . . 40 10.20.1 basic output configuration . . . . . . . . . . . . . . . 41 10.20.2 low input impedance iq-modulator interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.20.3 iq-modulator - dc interface. . . . . . . . . . . . . . 42 10.20.4 iq-modulator - ac interface . . . . . . . . . . . . . . 45 10.21 design recommendations . . . . . . . . . . . . . . . 45 10.21.1 power and grounding. . . . . . . . . . . . . . . . . . . 45 10.22 configuration interface. . . . . . . . . . . . . . . . . . 46 10.22.1 register description . . . . . . . . . . . . . . . . . . . . 46 10.22.2 spi start-up sequence . . . . . . . . . . . . . . . . . . 46 10.22.3 page 0 register allocation map . . . . . . . . . . . 48 10.22.4 page 0 bit definition detailed description . . . . 50 10.22.5 page 1 allocation map . . . . . . . . . . . . . . . . . . 55 10.22.6 page 1 bit definition detailed description . . . . 57 10.22.7 page a register allocation map . . . . . . . . . . . 65 10.22.8 page a bit definition detailed description . . . . 67 11 package outline. . . . . . . . . . . . . . . . . . . . . . . . 73 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 74 13 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 13.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 75 13.2 dynamic parameters . . . . . . . . . . . . . . . . . . . 75 14 revision history . . . . . . . . . . . . . . . . . . . . . . . 76 15 contact information . . . . . . . . . . . . . . . . . . . . 76 16 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 |
Price & Availability of DAC1617D1G0HN
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